OpenSTA/verilog
Jaehyun Kim 992a1dcec5 Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenSTA into secure-sta-test-by-opus
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-20 21:56:12 +09:00
..
test test: Fix post-merge build errors and regolden .ok files 2026-03-11 17:11:08 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy update copyright 2026-03-10 14:57:45 -07:00
VerilogReader.cc update copyright 2026-03-10 14:57:45 -07:00
VerilogReaderPvt.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogScanner.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogWriter.cc update copyright 2026-03-10 14:57:45 -07:00