15 lines
667 B
Verilog
15 lines
667 B
Verilog
// Verilog with bus port bit and part select connections
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// This triggers makeNetNamedPortRefBit and makeNetNamedPortRefPart
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module bus_mod (input [3:0] data_in, output [3:0] data_out);
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wire [3:0] w;
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// Named connections with bus references
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BUFx2_ASAP7_75t_R u0 (.A(data_in[0]), .Y(w[0]));
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BUFx2_ASAP7_75t_R u1 (.A(data_in[1]), .Y(w[1]));
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BUFx2_ASAP7_75t_R u2 (.A(data_in[2]), .Y(w[2]));
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BUFx2_ASAP7_75t_R u3 (.A(data_in[3]), .Y(w[3]));
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BUFx2_ASAP7_75t_R u4 (.A(w[0]), .Y(data_out[0]));
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BUFx2_ASAP7_75t_R u5 (.A(w[1]), .Y(data_out[1]));
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BUFx2_ASAP7_75t_R u6 (.A(w[2]), .Y(data_out[2]));
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BUFx2_ASAP7_75t_R u7 (.A(w[3]), .Y(data_out[3]));
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endmodule
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