390 lines
12 KiB
Plaintext
390 lines
12 KiB
Plaintext
library(fakeram7_256x32) {
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technology (cmos);
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delay_model : table_lookup;
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revision : 1.0;
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date : "2023-08-15 21:29:36Z";
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comment : "SRAM";
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time_unit : "1ns";
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voltage_unit : "1V";
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current_unit : "1uA";
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leakage_power_unit : "1uW";
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nom_process : 1;
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nom_temperature : 25.000;
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nom_voltage : 0.7;
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capacitive_load_unit (1,pf);
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pulling_resistance_unit : "1kohm";
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operating_conditions(tt_1.0_25.0) {
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process : 1;
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temperature : 25.000;
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voltage : 0.7;
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tree_type : balanced_tree;
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}
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/* default attributes */
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default_cell_leakage_power : 0;
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default_fanout_load : 1;
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default_inout_pin_cap : 0.0;
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default_input_pin_cap : 0.0;
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default_output_pin_cap : 0.0;
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default_input_pin_cap : 0.0;
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default_max_transition : 0.227;
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default_operating_conditions : tt_1.0_25.0;
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default_leakage_power_density : 0.0;
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/* additional header data */
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slew_derate_from_library : 1.000;
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slew_lower_threshold_pct_fall : 20.000;
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slew_upper_threshold_pct_fall : 80.000;
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slew_lower_threshold_pct_rise : 20.000;
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slew_upper_threshold_pct_rise : 80.000;
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input_threshold_pct_fall : 50.000;
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input_threshold_pct_rise : 50.000;
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output_threshold_pct_fall : 50.000;
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output_threshold_pct_rise : 50.000;
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lu_table_template(fakeram7_256x32_mem_out_delay_template) {
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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index_1 ("1000, 1001");
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index_2 ("1000, 1001");
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}
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lu_table_template(fakeram7_256x32_mem_out_slew_template) {
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variable_1 : total_output_net_capacitance;
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index_1 ("1000, 1001");
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}
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lu_table_template(fakeram7_256x32_constraint_template) {
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variable_1 : related_pin_transition;
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variable_2 : constrained_pin_transition;
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index_1 ("1000, 1001");
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index_2 ("1000, 1001");
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}
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power_lut_template(fakeram7_256x32_energy_template_clkslew) {
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variable_1 : input_transition_time;
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index_1 ("1000, 1001");
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}
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power_lut_template(fakeram7_256x32_energy_template_sigslew) {
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variable_1 : input_transition_time;
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index_1 ("1000, 1001");
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}
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library_features(report_delay_calculation);
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type (fakeram7_256x32_DATA) {
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base_type : array ;
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data_type : bit ;
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bit_width : 32;
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bit_from : 31;
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bit_to : 0 ;
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downto : true ;
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}
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type (fakeram7_256x32_ADDRESS) {
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base_type : array ;
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data_type : bit ;
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bit_width : 8;
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bit_from : 7;
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bit_to : 0 ;
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downto : true ;
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}
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cell(fakeram7_256x32) {
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area : 343.985;
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interface_timing : true;
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memory() {
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type : ram;
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address_width : 8;
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word_width : 32;
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}
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pin(clk) {
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direction : input;
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capacitance : 0.025;
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clock : true;
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min_period : 0.157 ;
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internal_power(){
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rise_power(fakeram7_256x32_energy_template_clkslew) {
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index_1 ("0.009, 0.227");
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values ("1.345, 1.345")
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}
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fall_power(fakeram7_256x32_energy_template_clkslew) {
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index_1 ("0.009, 0.227");
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values ("1.345, 1.345")
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}
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}
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}
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bus(rd_out) {
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bus_type : fakeram7_256x32_DATA;
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direction : output;
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max_capacitance : 0.500;
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memory_read() {
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address : addr_in;
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}
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timing() {
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related_pin : "clk" ;
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timing_type : rising_edge;
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timing_sense : non_unate;
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cell_rise(fakeram7_256x32_mem_out_delay_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.005, 0.500");
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values ( \
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"0.218, 0.218", \
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"0.218, 0.218" \
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)
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}
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cell_fall(fakeram7_256x32_mem_out_delay_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.005, 0.500");
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values ( \
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"0.218, 0.218", \
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"0.218, 0.218" \
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)
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}
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rise_transition(fakeram7_256x32_mem_out_slew_template) {
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index_1 ("0.005, 0.500");
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values ("0.009, 0.227")
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}
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fall_transition(fakeram7_256x32_mem_out_slew_template) {
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index_1 ("0.005, 0.500");
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values ("0.009, 0.227")
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}
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}
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}
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pin(we_in){
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direction : input;
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capacitance : 0.005;
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timing() {
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related_pin : clk;
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timing_type : setup_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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timing() {
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related_pin : clk;
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timing_type : hold_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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internal_power(){
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rise_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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fall_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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}
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}
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pin(ce_in){
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direction : input;
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capacitance : 0.005;
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timing() {
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related_pin : clk;
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timing_type : setup_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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timing() {
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related_pin : clk;
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timing_type : hold_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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internal_power(){
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rise_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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fall_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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}
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}
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bus(addr_in) {
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bus_type : fakeram7_256x32_ADDRESS;
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direction : input;
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capacitance : 0.005;
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timing() {
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related_pin : clk;
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timing_type : setup_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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timing() {
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related_pin : clk;
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timing_type : hold_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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internal_power(){
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rise_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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fall_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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}
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}
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bus(wd_in) {
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bus_type : fakeram7_256x32_DATA;
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memory_write() {
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address : addr_in;
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clocked_on : "clk";
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}
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direction : input;
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capacitance : 0.005;
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timing() {
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related_pin : clk;
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timing_type : setup_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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timing() {
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related_pin : clk;
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timing_type : hold_rising ;
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rise_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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fall_constraint(fakeram7_256x32_constraint_template) {
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index_1 ("0.009, 0.227");
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index_2 ("0.009, 0.227");
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values ( \
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"0.050, 0.050", \
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"0.050, 0.050" \
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)
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}
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}
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internal_power(){
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when : "(! (we_in) )";
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rise_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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fall_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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}
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internal_power(){
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when : "(we_in)";
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rise_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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fall_power(fakeram7_256x32_energy_template_sigslew) {
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index_1 ("0.009, 0.227");
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values ("0.013, 0.013")
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}
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}
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}
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cell_leakage_power : 128.900;
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}
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}
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