266 lines
7.5 KiB
C++
266 lines
7.5 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#include "GatedClk.hh"
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#include "FuncExpr.hh"
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#include "Liberty.hh"
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#include "PortDirection.hh"
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#include "Network.hh"
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#include "Graph.hh"
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#include "Sdc.hh"
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#include "Search.hh"
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namespace sta {
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GatedClk::GatedClk(const StaState *sta) :
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StaState(sta)
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{
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}
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bool
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GatedClk::isGatedClkEnable(Vertex *vertex) const
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{
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bool is_gated_clk_enable;
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const Pin *clk_pin;
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LogicValue logic_active_value;
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isGatedClkEnable(vertex,
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is_gated_clk_enable, clk_pin, logic_active_value);
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return is_gated_clk_enable;
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}
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void
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GatedClk::isGatedClkEnable(Vertex *enable_vertex,
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bool &is_gated_clk_enable,
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const Pin *&clk_pin,
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LogicValue &logic_active_value) const
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{
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is_gated_clk_enable = false;
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const Pin *enable_pin = enable_vertex->pin();
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const Instance *inst = network_->instance(enable_pin);
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LibertyPort *enable_port = network_->libertyPort(enable_pin);
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EvalPred *eval_pred = search_->evalPred();
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if (enable_port
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&& enable_port->direction()->isInput()
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&& !sdc_->isDisableClockGatingCheck(enable_pin)
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&& !sdc_->isDisableClockGatingCheck(inst)
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&& eval_pred->searchFrom(enable_vertex)) {
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FuncExpr *func = nullptr;
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Vertex *gclk_vertex = nullptr;
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VertexOutEdgeIterator edge_iter(enable_vertex, graph_);
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while (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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gclk_vertex = edge->to(graph_);
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if (edge->role() == TimingRole::combinational()
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&& eval_pred->searchTo(gclk_vertex)
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&& eval_pred->searchThru(edge)) {
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const Pin *gclk_pin = gclk_vertex->pin();
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LibertyPort *gclk_port = network_->libertyPort(gclk_pin);
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if (gclk_port) {
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func = gclk_port->function();
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if (func)
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break;
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}
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}
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}
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if (func
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&& search_->isClock(gclk_vertex)
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&& !search_->isClock(enable_vertex)) {
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FuncExprPortIterator clk_port_iter(func);
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while (clk_port_iter.hasNext()) {
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LibertyPort *clk_port = clk_port_iter.next();
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if (clk_port != enable_port) {
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bool is_clk_gate = false;
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isClkGatingFunc(func, enable_port, clk_port,
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is_clk_gate, logic_active_value);
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if (is_clk_gate) {
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clk_pin = network_->findPin(inst, clk_port);
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if (clk_pin
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&& !sdc_->isDisableClockGatingCheck(clk_pin)
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&& search_->isClock(graph_->pinLoadVertex(clk_pin))) {
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is_gated_clk_enable = true;
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break;
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}
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}
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}
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}
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}
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}
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}
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void
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GatedClk::gatedClkEnables(Vertex *clk_vertex,
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// Return value.
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PinSet &enable_pins)
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{
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const Pin *clk_pin = clk_vertex->pin();
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const Instance *inst = network_->instance(clk_pin);
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LibertyPort *clk_port = network_->libertyPort(clk_pin);
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EvalPred *eval_pred = search_->evalPred();
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if (clk_port
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&& !sdc_->isDisableClockGatingCheck(clk_pin)
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&& !sdc_->isDisableClockGatingCheck(inst)
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&& eval_pred->searchFrom(clk_vertex)) {
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FuncExpr *func = nullptr;
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Vertex *gclk_vertex = nullptr;
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VertexOutEdgeIterator edge_iter(clk_vertex, graph_);
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while (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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gclk_vertex = edge->to(graph_);
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if (edge->role() == TimingRole::combinational()
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&& eval_pred->searchTo(gclk_vertex)
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&& eval_pred->searchThru(edge)) {
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const Pin *gclk_pin = gclk_vertex->pin();
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LibertyPort *gclk_port = network_->libertyPort(gclk_pin);
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if (gclk_port) {
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func = gclk_port->function();
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if (func) {
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if (search_->isClock(gclk_vertex)) {
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FuncExprPortIterator enable_port_iter(func);
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while (enable_port_iter.hasNext()) {
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LibertyPort *enable_port = enable_port_iter.next();
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if (enable_port != clk_port) {
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bool is_clk_gate;
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LogicValue logic_value;
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isClkGatingFunc(func, enable_port, clk_port,
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is_clk_gate, logic_value);
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if (is_clk_gate) {
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Pin *enable_pin = network_->findPin(inst, enable_port);
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if (enable_pin
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&& !sdc_->isDisableClockGatingCheck(enable_pin)
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&& !search_->isClock(graph_->pinLoadVertex(enable_pin))) {
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enable_pins.insert(enable_pin);
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}
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}
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}
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}
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}
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break;
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}
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}
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}
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}
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}
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}
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void
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GatedClk::isClkGatingFunc(FuncExpr *func,
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LibertyPort *enable_port,
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LibertyPort *clk_port,
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bool &is_clk_gate,
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LogicValue &logic_value) const
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{
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// The function should be in two-level SOP or POS form depending on "cost".
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// We need to apply literal cofactor if any input port is constant and
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// do "simple" logic minimization based on SOP and POS.
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while (func->op() == FuncExpr::op_not)
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func = func->left();
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if (func->op() == FuncExpr::op_and)
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logic_value = LogicValue::one;
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else if (func->op() == FuncExpr::op_or)
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logic_value = LogicValue::zero;
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else {
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is_clk_gate = false;
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return;
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}
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FuncExprSet funcs;
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functionClkOperands(func, func->left(), funcs);
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functionClkOperands(func, func->right(), funcs);
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bool need_gating_check = false;
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FuncExprSet::Iterator expr_iter(funcs);
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while (expr_iter.hasNext()) {
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FuncExpr *expr = expr_iter.next();
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if (expr->op() == FuncExpr::op_not) {
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if (expr->left()->op() == FuncExpr::op_port
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&& expr->left()->port() == clk_port) {
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need_gating_check = true;
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logic_value = (logic_value == LogicValue::one) ? LogicValue::zero : LogicValue::one;
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}
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}
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else {
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if (expr->op() == FuncExpr::op_port
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&& expr->port() == clk_port) {
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need_gating_check = true;
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}
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}
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}
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if (need_gating_check) {
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FuncExprSet::Iterator expr_iter2(funcs);
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while (expr_iter2.hasNext()) {
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FuncExpr *expr = expr_iter2.next();
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FuncExprPortIterator en_port_iter(expr);
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while (en_port_iter.hasNext()) {
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LibertyPort *port = en_port_iter.next();
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if (port == enable_port) {
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is_clk_gate = true;
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return;
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}
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}
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}
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}
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is_clk_gate = false;
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}
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void
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GatedClk::functionClkOperands(FuncExpr *root_expr,
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FuncExpr *expr,
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FuncExprSet &funcs) const
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{
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if (expr->op() != root_expr->op())
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funcs.insert(expr);
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else {
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functionClkOperands(root_expr, expr->left(), funcs);
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functionClkOperands(root_expr, expr->right(), funcs);
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}
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}
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const RiseFall *
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GatedClk::gatedClkActiveTrans(LogicValue active_value,
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const MinMax *min_max) const
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{
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const RiseFall *leading_rf;
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switch (active_value) {
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case LogicValue::one:
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case LogicValue::unknown:
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leading_rf = RiseFall::rise();
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break;
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case LogicValue::zero:
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leading_rf = RiseFall::fall();
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break;
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default:
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criticalError(249, "illegal gated clock active value");
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leading_rf = RiseFall::rise();
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break;
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}
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if (min_max == MinMax::max())
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return leading_rf;
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else
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return leading_rf->opposite();
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}
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} // namespace
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