178 lines
5.4 KiB
Plaintext
178 lines
5.4 KiB
Plaintext
--- get_timing_edges -of_objects instance ---
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reg1 timing edges count: 1
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--- get_timing_edges -from/-to on instance ---
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CK->Q edges count: 1
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--- get_timing_edges -from only ---
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edges from CK count: 5
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--- get_timing_edges -to only ---
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edges to Q count: 1
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--- report_edges -from/-to ---
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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--- report_edges -from ---
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CK -> QN Reg Clk to Q
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^ -> ^ 0.06:0.06
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^ -> v 0.06:0.06
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CK -> Q Reg Clk to Q
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^ -> ^ 0.08:0.08
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^ -> v 0.08:0.08
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CK -> CK width
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^ -> v 0.05:0.05
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v -> ^ 0.05:0.05
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CK -> D setup
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^ -> ^ 0.03:0.03
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^ -> v 0.04:0.04
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CK -> D hold
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^ -> ^ 0.00:0.00
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^ -> v 0.00:0.00
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--- report_edges -to ---
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CK -> D setup
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^ -> ^ 0.03:0.03
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^ -> v 0.04:0.04
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CK -> D hold
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^ -> ^ 0.01:0.01
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^ -> v 0.00:0.00
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reg1/Q -> D wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- report_disabled_edges (baseline) ---
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--- set_disable_timing on instance ---
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--- report_disabled_edges after disable ---
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reg1 CK Q constraint
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reg1 CK QN constraint
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--- report_checks after disable ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ q (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- unset_disable_timing on instance ---
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--- report_disabled_edges after unset ---
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--- set_disable_timing with -from/-to on lib cell ---
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--- report_disabled_edges after lib cell disable ---
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reg1 CK Q constraint
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reg2 CK Q constraint
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--- unset_disable_timing lib cell ---
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--- report_checks baseline ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- report_checks -path_delay max ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- report_checks -path_delay min ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.00 0.00 ^ reg1/D (DFF_X1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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0.00 slack (VIOLATED)
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--- report_checks from d to q ---
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No paths found.
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--- report_edges -from port d ---
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d -> reg1/D wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- report_edges -to port q ---
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reg2/Q -> q wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- get_timing_edges -of_objects reg2 ---
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reg2 timing edges count: 1
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--- report_slews on d port ---
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d ^ 0.00:0.00 v 0.00:0.00
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--- report_slews on q port ---
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q ^ 0.01:0.01 v 0.00:0.00
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