183 lines
5.8 KiB
Tcl
183 lines
5.8 KiB
Tcl
# Test graph incremental changes, constant propagation, and level reporting.
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# Targets: Graph.cc/GraphCmp.cc/DelayFloat.cc graph update and traversal paths.
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog graph_test2.v
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link_design graph_test2
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports d1]
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set_input_delay -clock clk 1.0 [get_ports d2]
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set_input_delay -clock clk 0 [get_ports en]
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set_output_delay -clock clk 1.0 [get_ports q1]
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set_output_delay -clock clk 1.0 [get_ports q2]
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set_input_transition 0.1 [get_ports {d1 d2 en}]
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#---------------------------------------------------------------
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# Baseline timing
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#---------------------------------------------------------------
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puts "--- baseline report_checks ---"
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report_checks
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report_checks -path_delay min
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report_checks -path_delay max
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#---------------------------------------------------------------
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# Multiple paths through design
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#---------------------------------------------------------------
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puts "--- multiple paths ---"
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report_checks -from [get_ports d1] -to [get_ports q1]
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report_checks -from [get_ports d1] -to [get_ports q2]
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report_checks -from [get_ports d2] -to [get_ports q2]
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report_checks -from [get_ports en] -to [get_ports q1]
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report_checks -from [get_ports en] -to [get_ports q2]
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#---------------------------------------------------------------
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# -through paths (exercises graph traversal)
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#---------------------------------------------------------------
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puts "--- through paths ---"
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report_checks -through [get_pins inv1/ZN]
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puts "through inv1/ZN: done"
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report_checks -through [get_pins and1/ZN]
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puts "through and1/ZN: done"
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report_checks -through [get_pins or1/ZN]
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puts "through or1/ZN: done"
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report_checks -through [get_pins buf3/Z]
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puts "through buf3/Z: done"
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#---------------------------------------------------------------
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# Timing edge queries for multi-input cells
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#---------------------------------------------------------------
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puts "--- timing edges for multi-input cells ---"
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set edges_and [get_timing_edges -of_objects [get_cells and1]]
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puts "and1 edges: [llength $edges_and]"
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set edges_or [get_timing_edges -of_objects [get_cells or1]]
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puts "or1 edges: [llength $edges_or]"
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set edges_reg1 [get_timing_edges -of_objects [get_cells reg1]]
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puts "reg1 edges: [llength $edges_reg1]"
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set edges_reg2 [get_timing_edges -of_objects [get_cells reg2]]
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puts "reg2 edges: [llength $edges_reg2]"
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# From/to specific pins
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set edges_ft [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
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puts "and1 A1->ZN edges: [llength $edges_ft]"
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set edges_ft2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
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puts "and1 A2->ZN edges: [llength $edges_ft2]"
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set edges_ft3 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
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puts "or1 A1->ZN edges: [llength $edges_ft3]"
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#---------------------------------------------------------------
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# report_edges for various pin combinations
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#---------------------------------------------------------------
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puts "--- report_edges ---"
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report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
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report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
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report_edges -from [get_pins and1/A1]
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report_edges -to [get_pins and1/ZN]
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report_edges -from [get_ports d1]
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report_edges -to [get_ports q2]
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#---------------------------------------------------------------
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# Constant propagation via set_case_analysis
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#---------------------------------------------------------------
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puts "--- set_case_analysis ---"
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set_case_analysis 1 [get_ports en]
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report_checks
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report_checks -from [get_ports d1] -to [get_ports q1]
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# Change constant value
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set_case_analysis 0 [get_ports en]
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report_checks
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# Remove case analysis
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unset_case_analysis [get_ports en]
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report_checks
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#---------------------------------------------------------------
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# Disable/enable timing with multiple cells
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#---------------------------------------------------------------
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puts "--- disable/enable timing multiple cells ---"
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set_disable_timing [get_cells buf1]
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report_checks
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set_disable_timing [get_cells inv1]
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report_checks
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unset_disable_timing [get_cells buf1]
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report_checks
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unset_disable_timing [get_cells inv1]
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report_checks
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# Disable specific lib cell arc
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set_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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report_disabled_edges
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report_checks
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unset_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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report_disabled_edges
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report_checks
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#---------------------------------------------------------------
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# report_check_types
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#---------------------------------------------------------------
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puts "--- report_check_types ---"
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report_check_types -max_delay -verbose
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report_check_types -min_delay -verbose
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report_check_types -max_delay -min_delay -verbose
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#---------------------------------------------------------------
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# Report slews for various pins
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#---------------------------------------------------------------
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puts "--- report_slews ---"
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report_slews [get_ports d1]
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report_slews [get_ports d2]
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report_slews [get_ports en]
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report_slews [get_ports q1]
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report_slews [get_ports q2]
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report_slews [get_pins buf1/Z]
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report_slews [get_pins inv1/ZN]
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report_slews [get_pins and1/ZN]
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report_slews [get_pins or1/ZN]
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report_slews [get_pins reg1/Q]
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report_slews [get_pins reg2/Q]
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#---------------------------------------------------------------
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# report_checks with -unconstrained
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#---------------------------------------------------------------
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puts "--- report_checks -unconstrained ---"
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report_checks -unconstrained
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#---------------------------------------------------------------
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# report_checks with group_count and endpoint_count
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#---------------------------------------------------------------
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puts "--- report_checks counts ---"
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report_checks -group_count 3
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report_checks -endpoint_count 3
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report_checks -endpoint_count 5 -path_delay min
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