17 lines
538 B
Verilog
17 lines
538 B
Verilog
module sdc_test2 (clk1, clk2, in1, in2, in3, out1, out2);
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input clk1, clk2, in1, in2, in3;
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output out1, out2;
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wire n1, n2, n3, n4, n5, n6, n7;
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BUF_X1 buf1 (.A(in1), .Z(n1));
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INV_X1 inv1 (.A(in2), .ZN(n2));
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AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n3));
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OR2_X1 or1 (.A1(n1), .A2(in3), .ZN(n4));
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NAND2_X1 nand1 (.A1(n3), .A2(n4), .ZN(n5));
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NOR2_X1 nor1 (.A1(n3), .A2(n4), .ZN(n6));
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DFF_X1 reg1 (.D(n5), .CK(clk1), .Q(n7));
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DFF_X1 reg2 (.D(n6), .CK(clk1), .Q(out1));
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DFF_X1 reg3 (.D(n7), .CK(clk2), .Q(out2));
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endmodule
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