35 lines
1.1 KiB
Verilog
35 lines
1.1 KiB
Verilog
// Larger design for graph operations testing: more cell types, fan-in/fan-out,
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// multiple clock domains, and reconvergent paths.
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module graph_test3 (clk1, clk2, rst, d1, d2, d3, d4, q1, q2, q3);
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input clk1, clk2, rst, d1, d2, d3, d4;
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output q1, q2, q3;
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wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
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// Input stage: buffers and inverters
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BUF_X1 buf1 (.A(d1), .Z(n1));
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BUF_X2 buf2 (.A(d2), .Z(n2));
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INV_X1 inv1 (.A(d3), .ZN(n3));
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INV_X2 inv2 (.A(d4), .ZN(n4));
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// Middle stage: logic gates
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AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
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OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n6));
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NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
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NOR2_X1 nor1 (.A1(n1), .A2(n3), .ZN(n8));
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// Reconvergent fan-out
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AND2_X2 and2 (.A1(n7), .A2(n8), .ZN(n9));
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OR2_X2 or2 (.A1(n7), .A2(n8), .ZN(n10));
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// Clock domain 1 registers
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DFF_X1 reg1 (.D(n9), .CK(clk1), .Q(n11));
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DFF_X1 reg2 (.D(n10), .CK(clk1), .Q(q1));
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// Clock domain 2 register (cross-domain)
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DFF_X1 reg3 (.D(n11), .CK(clk2), .Q(n12));
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BUF_X1 buf3 (.A(n12), .Z(q2));
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// Combinational output
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BUF_X4 buf4 (.A(n7), .Z(q3));
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endmodule
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