139 lines
4.8 KiB
Plaintext
139 lines
4.8 KiB
Plaintext
--- report_check_types -min_period (non-verbose = short) ---
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--- report_check_types -min_period -verbose ---
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--- report_check_types -min_period -violators ---
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--- report_check_types -min_period -violators -verbose ---
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--- min_period_check_slack short ---
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min_period_check_slack: skipped (API removed)
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--- min_period_violations short/verbose ---
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min_period_violations: skipped (API removed)
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--- max_skew_check_slack ---
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max_skew_check_slack: skipped (API removed)
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--- max_skew_violations ---
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max_skew_violations: skipped (API removed)
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--- report_check_types -max_skew (short) ---
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--- report_check_types -max_skew -verbose ---
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--- report_check_types all with tight clock ---
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.20 0.01 0.19 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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buf1/Z 60.65 1.14 59.51 (MET)
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 0.02 -0.03 (VIOLATED)
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max slew
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Pin reg1/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin buf1/Z ^
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max capacitance 60.65
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capacitance 1.14
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-----------------------
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Slack 59.51 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock fast_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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0.02 0.02 clock fast_clk (fall edge)
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0.00 0.02 clock network delay (ideal)
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0.00 0.02 reg1/CK
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0.00 0.02 clock reconvergence pessimism
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0.02 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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0.02 actual pulse width
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---------------------------------------------------------
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-0.03 slack (VIOLATED)
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--- report_check_types -violators ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 0.02 -0.03 (VIOLATED)
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reg1/CK (low) 0.05 0.02 -0.03 (VIOLATED)
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--- report_clock_min_period ---
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fast_clk period_min = 0.00 fmax = inf
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fast_clk period_min = 0.00 fmax = inf
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fast_clk period_min = 0.11 fmax = 9067.34
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--- Now with normal clock period ---
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--- report_check_types with normal clock ---
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--- min_pulse_width short and verbose ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock normal_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock normal_clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock normal_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock normal_clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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