231 lines
8.0 KiB
Tcl
231 lines
8.0 KiB
Tcl
# Test operating conditions, scale factors, and multi-corner features.
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# Targets:
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# Liberty.cc: findOperatingConditions, defaultOperatingConditions,
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# scaleFactor (all overloads), addScaleFactors, findScaleFactors,
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# inverters(), buffers(), makeCornerMap, setDelayModelType,
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# findLibertyCellsMatching, findLibertyPortsMatching,
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# ocvArcDepth, defaultOcvDerate, supplyVoltage, supplyExists,
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# slewDerateFromLibrary, input/output/slewThresholds,
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# defaultMaxFanout/Slew/Capacitance, defaultFanoutLoad,
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# defaultIntrinsic, defaultPinResistance, footprint
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# LibertyReader.cc: operating_conditions, scale_factors visitor paths
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# EquivCells.cc: EquivCells constructor with map_libs path
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source ../../test/helpers.tcl
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############################################################
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# Read Nangate45 library - has operating conditions
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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set lib [sta::find_liberty NangateOpenCellLibrary]
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############################################################
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# Operating conditions queries
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############################################################
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set op_cond [$lib find_operating_conditions typical]
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if { $op_cond == "NULL" } {
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puts "INFO: no operating_conditions named typical"
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}
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set def_op [$lib default_operating_conditions]
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if { $def_op == "NULL" } {
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puts "INFO: no default operating conditions"
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}
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############################################################
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# Set operating conditions and run timing
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############################################################
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read_verilog ../../sdc/test/sdc_test2.v
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link_design sdc_test2
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 [get_ports clk2]
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set_input_delay -clock clk1 2.0 [all_inputs]
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set_output_delay -clock clk1 3.0 [all_outputs]
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set_input_transition 0.1 [all_inputs]
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set_operating_conditions typical
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report_checks -from [get_ports in1] -to [get_ports out1]
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############################################################
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# Library cell classification queries
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# Exercises: inverters(), buffers(), isBuffer(), isInverter()
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############################################################
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set inv_cell [sta::find_liberty_cell INV_X1]
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set buf_cell [sta::find_liberty_cell BUF_X1]
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set inv_is_inv [$inv_cell is_inverter]
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set inv_is_buf [$inv_cell is_buffer]
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set buf_is_buf [$buf_cell is_buffer]
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set buf_is_inv [$buf_cell is_inverter]
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# Test is_leaf on various cells
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set dff_cell [sta::find_liberty_cell DFF_X1]
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set dff_leaf [$dff_cell is_leaf]
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# Liberty library accessor on cell
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set cell_lib [$inv_cell liberty_library]
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############################################################
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# Pattern matching on liberty cells
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# Exercises: findLibertyCellsMatching, findLibertyPortsMatching
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############################################################
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set inv_matches [$lib find_liberty_cells_matching "INV*" 0 0]
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set buf_matches [$lib find_liberty_cells_matching "BUF*" 0 0]
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set dff_matches [$lib find_liberty_cells_matching "DFF*" 0 0]
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set sdff_matches [$lib find_liberty_cells_matching "SDFF*" 0 0]
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set all_matches [$lib find_liberty_cells_matching "*" 0 0]
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# Port pattern matching
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set inv_port_matches [$inv_cell find_liberty_ports_matching "*" 0 0]
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set dff_port_matches [$dff_cell find_liberty_ports_matching "*" 0 0]
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############################################################
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# Timing arc queries on cells
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# Exercises: timingArcSets, timingArcSetCount, hasTimingArcs
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############################################################
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set inv_arc_sets [$inv_cell timing_arc_sets]
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set dff_arc_sets [$dff_cell timing_arc_sets]
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# Check timing arc set ports
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set clkgate_cell [sta::find_liberty_cell CLKGATETST_X1]
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set clkgate_arcs [$clkgate_cell timing_arc_sets]
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############################################################
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# Find port on liberty cell
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# Exercises: findLibertyPort
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############################################################
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set inv_a [$inv_cell find_liberty_port A]
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set inv_zn [$inv_cell find_liberty_port ZN]
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set dff_ck [$dff_cell find_liberty_port CK]
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set dff_d [$dff_cell find_liberty_port D]
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set dff_q [$dff_cell find_liberty_port Q]
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############################################################
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# Liberty port iterator on cell
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# Exercises: LibertyCellPortIterator
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############################################################
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set port_iter [$inv_cell liberty_port_iterator]
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set count 0
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while { [$port_iter has_next] } {
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set port [$port_iter next]
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incr count
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}
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$port_iter finish
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set port_iter2 [$dff_cell liberty_port_iterator]
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set count2 0
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while { [$port_iter2 has_next] } {
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set port [$port_iter2 next]
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incr count2
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}
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$port_iter2 finish
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############################################################
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# Wireload queries
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# Exercises: findWireload, findWireloadSelection
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############################################################
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set wl [$lib find_wireload "1K_hvratio_1_1"]
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if { $wl == "NULL" } {
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puts "INFO: wireload not found"
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}
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set wls [$lib find_wireload_selection "WireloadSelection"]
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if { $wls == "NULL" } {
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puts "INFO: wireload selection not found"
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}
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############################################################
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# Read Sky130 library - has different features
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############################################################
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
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set sky_op [$sky_lib find_operating_conditions "tt_025C_1v80"]
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if { $sky_op == "NULL" } {
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puts "INFO: sky130 no named operating conditions"
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}
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set sky_def_op [$sky_lib default_operating_conditions]
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if { $sky_def_op == "NULL" } {
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puts "INFO: sky130 no default operating conditions"
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}
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############################################################
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# Read fast/slow libraries for multi-corner analysis
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# Exercises: makeCornerMap path, setCornerCell, scaleFactor
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############################################################
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read_liberty ../../test/nangate45/Nangate45_fast.lib
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# Read slow too - exercises more corner mapping paths
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
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# Report checks exercises multi-library corner paths
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report_checks -from [get_ports in1] -to [get_ports out1]
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############################################################
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# set_timing_derate - exercises OCV paths
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############################################################
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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report_checks -from [get_ports in1] -to [get_ports out1]
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############################################################
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# Write liberty for Nangate to exercise all writer paths
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############################################################
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set outfile [make_result_file liberty_opcond_scale_write.lib]
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sta::write_liberty NangateOpenCellLibrary $outfile
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set outfile2 [make_result_file liberty_opcond_scale_sky130.lib]
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sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
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############################################################
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# EquivCells with multiple libraries
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# Exercises: EquivCells constructor with map_libs
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############################################################
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set lib1 [lindex [get_libs NangateOpenCellLibrary] 0]
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set lib2 [lindex [get_libs NangateOpenCellLibrary_fast] 0]
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sta::make_equiv_cells $lib1
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sta::make_equiv_cells $lib2
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# Cross-library equiv
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set inv_typ [get_lib_cell NangateOpenCellLibrary/INV_X1]
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set inv_fast [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
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set result [sta::equiv_cells $inv_typ $inv_fast]
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set buf_typ [get_lib_cell NangateOpenCellLibrary/BUF_X1]
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set buf_fast [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
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set result [sta::equiv_cells $buf_typ $buf_fast]
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# equiv_cell_ports across libraries
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set result [sta::equiv_cell_ports $inv_typ $inv_fast]
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# equiv_cell_timing_arcs across libraries
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set result [sta::equiv_cell_timing_arcs $inv_typ $inv_fast]
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############################################################
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# Report check types for max_cap, max_slew, max_fanout
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############################################################
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report_check_types -max_slew -max_capacitance -max_fanout -verbose
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