190 lines
4.4 KiB
Plaintext
190 lines
4.4 KiB
Plaintext
--- voltage_map / supply queries ---
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VPWR exists: 1
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VGND exists: 1
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VPB exists: 1
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VNB exists: 1
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KAPWR exists: 1
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LOWLVPWR exists: 1
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VPWRIN exists: 1
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VSS exists: 1
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FAKE_SUPPLY exists: 0
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--- clock gate cell queries ---
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sky130_fd_sc_hd__dlclkp_1 area=17.516800
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Cell sky130_fd_sc_hd__dlclkp_1
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Library sky130_fd_sc_hd__tt_025C_1v80
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File ../../test/sky130hd/sky130hd_tt.lib
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VGND ground
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VNB well
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VPB well
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VPWR power
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CLK input 0.00-0.00
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GATE input 0.00-0.00
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GCLK output
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M0 internal
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Timing arcs
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CLK -> CLK
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width
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v -> ^
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CLK -> GATE
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setup
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^ -> ^
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^ -> v
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CLK -> GATE
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hold
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^ -> ^
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^ -> v
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CLK -> GCLK
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combinational
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^ -> ^
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v -> v
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sky130_fd_sc_hd__dlclkp_2 area=18.768000
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Cell sky130_fd_sc_hd__dlclkp_2
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Library sky130_fd_sc_hd__tt_025C_1v80
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File ../../test/sky130hd/sky130hd_tt.lib
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VGND ground
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VNB well
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VPB well
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VPWR power
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CLK input 0.00-0.00
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GATE input 0.00-0.00
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GCLK output
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M0 internal
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Timing arcs
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CLK -> CLK
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width
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v -> ^
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CLK -> GATE
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setup
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^ -> ^
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^ -> v
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CLK -> GATE
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hold
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^ -> ^
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^ -> v
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CLK -> GCLK
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combinational
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^ -> ^
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v -> v
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sky130_fd_sc_hd__dlclkp_4 area=21.270399
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Cell sky130_fd_sc_hd__dlclkp_4
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Library sky130_fd_sc_hd__tt_025C_1v80
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File ../../test/sky130hd/sky130hd_tt.lib
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VGND ground
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VNB well
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VPB well
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VPWR power
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CLK input 0.00-0.01
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GATE input 0.00-0.00
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GCLK output
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M0 internal
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Timing arcs
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CLK -> CLK
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width
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v -> ^
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CLK -> GATE
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setup
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^ -> ^
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^ -> v
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CLK -> GATE
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hold
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^ -> ^
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^ -> v
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CLK -> GCLK
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combinational
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^ -> ^
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v -> v
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sky130_fd_sc_hd__sdlclkp_1 area=18.768000
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VGND dir=ground func=
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VNB dir=well func=
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VPB dir=well func=
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VPWR dir=power func=
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CLK dir=input func=
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GATE dir=input func=
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GCLK dir=output func=
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M0 dir=internal func=
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SCE dir=input func=
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sky130_fd_sc_hd__sdlclkp_2 area=20.019199
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VGND dir=ground func=
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VNB dir=well func=
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VPB dir=well func=
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VPWR dir=power func=
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CLK dir=input func=
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GATE dir=input func=
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GCLK dir=output func=
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M0 dir=internal func=
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SCE dir=input func=
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sky130_fd_sc_hd__sdlclkp_4 area=22.521601
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VGND dir=ground func=
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VNB dir=well func=
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VPB dir=well func=
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VPWR dir=power func=
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CLK dir=input func=
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GATE dir=input func=
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GCLK dir=output func=
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M0 dir=internal func=
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SCE dir=input func=
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--- level shifter cell queries ---
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sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 area=35.033600
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 area=35.033600
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 area=40.038399
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 area=40.038399
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 area=35.033600
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 area=35.033600
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A dir=input
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X dir=output
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sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 area=40.038399
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A dir=input
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X dir=output
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--- pg_pin queries ---
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sky130_fd_sc_hd__inv_1: pwr_pins=4 signal_pins=2
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sky130_fd_sc_hd__buf_1: pwr_pins=4 signal_pins=2
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sky130_fd_sc_hd__nand2_1: pwr_pins=4 signal_pins=3
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sky130_fd_sc_hd__dfxtp_1: pwr_pins=4 signal_pins=5
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sky130_fd_sc_hd__dlclkp_1: pwr_pins=4 signal_pins=4
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sky130_fd_sc_hd__sdfxtp_1: pwr_pins=4 signal_pins=7
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--- clock gate timing arcs ---
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dlclkp_1 arc_sets = 4
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CLK -> CLK role=width
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CLK -> GATE role=setup
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CLK -> GATE role=hold
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CLK -> GCLK role=combinational
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sdlclkp_1 arc_sets = 6
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CLK -> CLK role=width
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CLK -> GATE role=setup
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CLK -> GATE role=hold
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CLK -> GCLK role=combinational
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CLK -> SCE role=setup
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CLK -> SCE role=hold
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--- level shifter timing arcs ---
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lsbuf_lh_hl_isowell_tap_1 arcs = 1
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A -> X role=combinational
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--- cell classification ---
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sky130_fd_sc_hd__inv_1: is_buffer=0 is_inverter=1 is_leaf=1
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sky130_fd_sc_hd__inv_2: is_buffer=0 is_inverter=1 is_leaf=1
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sky130_fd_sc_hd__buf_1: is_buffer=1 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__buf_2: is_buffer=1 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__clkinv_1: is_buffer=0 is_inverter=1 is_leaf=1
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sky130_fd_sc_hd__clkbuf_1: is_buffer=1 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__nand2_1: is_buffer=0 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__nor2_1: is_buffer=0 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__dfxtp_1: is_buffer=0 is_inverter=0 is_leaf=1
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sky130_fd_sc_hd__dlclkp_1: is_buffer=0 is_inverter=0 is_leaf=1
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IHP VDD exists: 0
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IHP sg13g2_inv_1: area=5.443200 buf=0 inv=1
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IHP sg13g2_buf_1: area=7.257600 buf=1 inv=0
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IHP sg13g2_nand2_1: area=7.257600 buf=0 inv=0
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IHP sg13g2_nor2_1: area=7.257600 buf=0 inv=0
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