module verilog_test1 (clk,
in1,
out1);
input clk;
input in1;
output out1;
wire extra_wire;
wire n1;
BUF_X1 buf1 (.A(in1),
.Z(n1));
INV_X1 extra_inv (.A(extra_wire));
DFF_X1 reg1 (.D(n1),
.CK(clk),
.Q(out1));
endmodule