377 lines
18 KiB
Plaintext
377 lines
18 KiB
Plaintext
--- read_sdf test3 (edge specifiers, RECOVERY/REMOVAL/PERIOD) ---
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--- report_annotated_delay combinations ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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18 12 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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----------------------------------------------------------------
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8 8 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 5 4 1
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----------------------------------------------------------------
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5 4 1
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 3 0 3
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----------------------------------------------------------------
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3 0 3
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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2 0 2
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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----------------------------------------------------------------
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13 12 1
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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18 12 6
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> reg1/D
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> inv1/A
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> and1/A1
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internal net inv1/ZN -> or1/A2
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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18 12 6
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net d -> buf1/A
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primary input net en -> and1/A2
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internal net buf1/Z -> or1/A1
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primary output net reg1/Q -> q
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primary output net reg1/QN -> q_inv
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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constant arcs 0 0
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internal net arcs 5 4 1
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constant arcs 0 0
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net arcs from primary inputs 3 0 3
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constant arcs 0 0
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net arcs to primary outputs 2 0 2
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constant arcs 0 0
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----------------------------------------------------------------
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18 12 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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18 12 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 8 8 0
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internal net arcs 5 4 1
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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18 12 6
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--- report_annotated_check combinations ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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2 2 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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2 2 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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Annotated Arcs
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width reg1/CK -> reg1/CK
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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Unannotated Arcs
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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constant arcs 0 0
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cell hold arcs 1 1 0
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constant arcs 0 0
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cell width arcs 1 1 0
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constant arcs 0 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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--- write_sdf various options ---
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--- report_checks with SDF annotations ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.14 0.41 v and1/ZN (AND2_X1)
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0.03 0.44 v reg1/D (DFF_X1)
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0.44 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.44 data arrival time
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---------------------------------------------------------
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9.53 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.05 0.05 ^ and1/ZN (AND2_X1)
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0.01 0.06 ^ reg1/D (DFF_X1)
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0.06 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.03 0.03 library hold time
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0.03 data required time
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---------------------------------------------------------
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0.03 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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0.03 slack (MET)
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.14 0.41 v and1/ZN (AND2_X1)
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0.03 0.44 v reg1/D (DFF_X1)
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0.44 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.44 data arrival time
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---------------------------------------------------------
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9.53 slack (MET)
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.14 0.41 v and1/ZN (AND2_X1)
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0.03 0.44 v reg1/D (DFF_X1)
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0.44 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.44 data arrival time
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---------------------------------------------------------
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9.53 slack (MET)
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.97 0.00 0.00 0.00 ^ d (in)
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0.00 0.00 0.00 ^ buf1/A (BUF_X1)
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2.65 0.01 0.15 0.15 ^ buf1/Z (BUF_X1)
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0.01 0.03 0.18 ^ inv1/A (INV_X1)
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1.77 0.00 0.09 0.27 v inv1/ZN (INV_X1)
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0.00 0.02 0.29 v and1/A1 (AND2_X1)
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1.06 0.01 0.12 0.41 v and1/ZN (AND2_X1)
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0.01 0.03 0.44 v reg1/D (DFF_X1)
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0.44 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------
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9.97 data required time
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-0.44 data arrival time
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-----------------------------------------------------------------------
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9.53 slack (MET)
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No paths found.
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No paths found.
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