OpenSTA/verilog
Jaehyun Kim 8adbcc0d6d Merge upstream STA update and adapt all tests to new API
Major upstream refactoring: Corner→Scene, Mode architecture, warning
format change (Warning ID:), command renames, and many API signature
changes. Adapted all C++ test files and TCL test scripts/expected
output files to pass with the new API. 6159/6159 tests pass.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 23:05:29 +09:00
..
test Merge upstream STA update and adapt all tests to new API 2026-02-23 23:05:29 +09:00
Verilog.i rel 3.0 2026-01-13 09:36:45 -07:00
Verilog.tcl rel 3.0 2026-01-13 09:36:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReader.cc rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReaderPvt.hh rel 3.0 2026-01-13 09:36:45 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rel 3.0 2026-01-13 09:36:45 -07:00