169 lines
5.8 KiB
Plaintext
169 lines
5.8 KiB
Plaintext
Warning: one2one.lib line 53, timing port A and related port Y are different sizes.
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Warning: one2one.lib line 68, timing port B and related port Y are different sizes.
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Warning: one2one.lib line 101, timing port A and related port Y are different sizes.
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Warning: one2one.lib line 116, timing port B and related port Y are different sizes.
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TEST 1:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[10] (input port clocked by clk)
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Endpoint: y[10] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[10] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20)
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0.00 1.00 ^ y[10] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[11] (input port clocked by clk)
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Endpoint: y[11] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[11] (in)
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1.00 1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20)
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0.00 1.00 ^ y[11] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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TEST 2:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ wide_or_cell/Y[0] (or_20_to_32)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[10] (input port clocked by clk)
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Endpoint: y[10] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[10] (in)
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1.00 1.00 ^ wide_or_cell/Y[10] (or_20_to_32)
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0.00 1.00 ^ y[10] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[11] (input port clocked by clk)
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Endpoint: y[11] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[11] (in)
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1.00 1.00 ^ wide_or_cell/Y[11] (or_20_to_32)
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0.00 1.00 ^ y[11] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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