411 lines
16 KiB
Plaintext
411 lines
16 KiB
Plaintext
--- get_cells with wildcard * ---
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buf* cells: 1
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--- get_cells with ? wildcard ---
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buf? cells: 1
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--- get_cells exact match ---
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buf1 cells: 1
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--- get_cells * ---
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* cells: 3
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--- get_pins with wildcards ---
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buf1/* pins: 2
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buf1/? pins: 2
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*/* pins: 10
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--- get_ports with wildcards ---
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*1 ports: 2
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* ports: 3
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--- get_nets with wildcards ---
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n* nets: 2
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--- non-matching patterns ---
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Warning: util_pattern_string.tcl line 1, instance 'zzz_nonexistent' not found.
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get_cells nonexistent: rc=0
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Warning: util_pattern_string.tcl line 1, pin 'zzz_nonexistent/*' not found.
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get_pins nonexistent: rc=0
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--- get_lib_cells with wildcards ---
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BUF* lib_cells: 6
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DFF_X? lib_cells: 2
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* lib_cells: 134
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--- set_debug with level > 0 ---
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delay_calc: delays invalid
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delay_calc: find delays to level 50
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delay_calc: found 9 delays
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search: find arrivals pass 1
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search: find arrivals to level 50
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search: arrival seed clk clk pin clk
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search: arrival seed input arrival in1
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search: find arrivals buf1/A
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search: in1
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search: ^ -> ^ min
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search: from tag: 4 ^ min/0 clk ^ clk_src clk crpr_pin null input in1
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 < MIA
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search: in1
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search: ^ -> ^ max
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search: from tag: 6 ^ max/1 clk ^ clk_src clk crpr_pin null input in1
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 > MIA
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search: in1
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search: v -> v min
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search: from tag: 5 v min/0 clk ^ clk_src clk crpr_pin null input in1
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 < MIA
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search: in1
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search: v -> v max
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search: from tag: 7 v max/1 clk ^ clk_src clk crpr_pin null input in1
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 > MIA
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search: find arrivals reg1/CK
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search: clk
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search: ^ -> ^ min
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search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 < MIA
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search: clk
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search: ^ -> ^ max
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search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: 0.000 + 0.000 = 0.000 > MIA
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search: clk
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search: v -> v min
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search: from tag: 1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
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search: to tag : 1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
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search: 5.000 + 0.000 = 5.000 < MIA
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search: clk
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search: v -> v max
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search: from tag: 3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
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search: to tag : 3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
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search: 5.000 + 0.000 = 5.000 > MIA
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search: find arrivals reg1/Q
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search: reg1/CK
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search: ^ -> ^ min
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search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.081 = 0.081 < MIA
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search: reg1/CK
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search: ^ -> v min
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search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.075 = 0.075 < MIA
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search: reg1/CK
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search: ^ -> ^ max
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search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.081 = 0.081 > MIA
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search: reg1/CK
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search: ^ -> v max
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search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.075 = 0.075 > MIA
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search: find arrivals reg1/QN
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search: reg1/CK
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search: ^ -> ^ min
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search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.056 = 0.056 < MIA
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search: reg1/CK
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search: ^ -> v min
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search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.057 = 0.057 < MIA
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search: reg1/CK
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search: ^ -> ^ max
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search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.056 = 0.056 > MIA
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search: reg1/CK
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search: ^ -> v max
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search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.057 = 0.057 > MIA
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search: find arrivals buf1/Z
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search: buf1/A
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search: ^ -> ^ min
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search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.018 = 0.018 < MIA
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search: buf1/A
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search: ^ -> ^ max
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search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.018 = 0.018 > MIA
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search: buf1/A
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search: v -> v min
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search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.022 = 0.022 < MIA
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search: buf1/A
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search: v -> v max
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search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.000 + 0.022 = 0.022 > MIA
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search: find arrivals inv1/A
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search: buf1/Z
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search: ^ -> ^ min
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search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.018 + 0.000 = 0.018 < MIA
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search: buf1/Z
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search: ^ -> ^ max
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search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.018 + 0.000 = 0.018 > MIA
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search: buf1/Z
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search: v -> v min
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search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.022 + 0.000 = 0.022 < MIA
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search: buf1/Z
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search: v -> v max
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search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.022 + 0.000 = 0.022 > MIA
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search: find arrivals out1
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search: reg1/Q
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search: ^ -> ^ min
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search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.081 + 0.000 = 0.081 < MIA
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search: reg1/Q
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search: ^ -> ^ max
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search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.081 + 0.000 = 0.081 > MIA
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search: reg1/Q
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search: v -> v min
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search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.075 + 0.000 = 0.075 < MIA
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search: reg1/Q
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search: v -> v max
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search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.075 + 0.000 = 0.075 > MIA
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search: find arrivals inv1/ZN
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search: inv1/A
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search: ^ -> v min
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search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.018 + 0.006 = 0.024 < MIA
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search: inv1/A
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search: ^ -> v max
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search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.018 + 0.006 = 0.024 > MIA
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search: inv1/A
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search: v -> ^ min
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search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.022 + 0.010 = 0.032 < MIA
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search: inv1/A
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search: v -> ^ max
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search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.022 + 0.010 = 0.032 > MIA
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search: find arrivals reg1/D
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search: inv1/ZN
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search: ^ -> ^ min
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search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
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search: 0.032 + 0.000 = 0.032 < MIA
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search: inv1/ZN
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search: ^ -> ^ max
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search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
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search: 0.032 + 0.000 = 0.032 > MIA
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search: inv1/ZN
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search: v -> v min
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search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
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search: 0.024 + 0.000 = 0.024 < MIA
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search: inv1/ZN
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search: v -> v max
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search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
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search: 0.024 + 0.000 = 0.024 > MIA
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search: found 9 arrivals
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search: find end slack reg1/D
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search: find end slack reg1/QN
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search: find end slack out1
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- FileNotWritable error path ---
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--- report_checks with rise/fall fields ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.88 0.15 0.00 0.00 v in1 (in)
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1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
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1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
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0.01 0.00 0.08 ^ reg1/D (DFF_X1)
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0.08 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------
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9.97 data required time
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-0.08 data arrival time
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-----------------------------------------------------------------------
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9.89 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.97 0.20 0.00 0.00 ^ in1 (in)
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0.20 0.00 0.00 ^ buf1/A (BUF_X1)
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1.70 0.01 0.03 0.03 ^ buf1/Z (BUF_X1)
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0.01 0.00 0.03 ^ inv1/A (INV_X1)
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1.06 0.00 0.01 0.04 v inv1/ZN (INV_X1)
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0.00 0.00 0.04 v reg1/D (DFF_X1)
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0.04 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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-----------------------------------------------------------------------
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0.00 data required time
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-0.04 data arrival time
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-----------------------------------------------------------------------
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0.04 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.88 0.15 0.00 0.00 v in1 (in)
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0.15 0.00 0.00 v buf1/A (BUF_X1)
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1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
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0.01 0.00 0.07 v inv1/A (INV_X1)
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1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
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0.01 0.00 0.08 ^ reg1/D (DFF_X1)
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0.08 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------
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9.97 data required time
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-0.08 data arrival time
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-----------------------------------------------------------------------
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9.89 slack (MET)
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--- set_load rise/fall ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.07 0.07 v buf1/Z (BUF_X1)
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0.01 0.08 ^ inv1/ZN (INV_X1)
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0.00 0.08 ^ reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.89 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.07 0.07 v buf1/Z (BUF_X1)
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0.01 0.08 ^ inv1/ZN (INV_X1)
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0.00 0.08 ^ reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.89 slack (MET)
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--- with_output_to_variable nesting ---
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v1 captured 984 chars
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v2 captured 1967 chars
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--- redirect_string with reports ---
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redirect string: 1414 chars
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