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7fdc304e12
* Add read_vcd -begin_time/-end_time activity windowing. Limit VCD transition and duty counting to an optional time window so activity annotation can ignore regions outside the interval of interest. Co-authored-by: Cursor <[email protected]> * Format VcdCount::setFilter parameters one per line. Co-authored-by: Cursor <[email protected]> * Address VCD begin/end review: VcdTime, sentinel, rename. Use VcdTime and vcd_null_time instead of int64_t/-1, rename VcdCount filter bounds to begin/end_time, rename the regression to vcd_begin_end_time, and document read_vcd -begin_time/-end_time in ChangeLog.txt. Co-authored-by: Cursor <[email protected]> --------- Co-authored-by: Cursor <[email protected]> Co-authored-by: James Cherry <[email protected]>
15 lines
172 B
Verilog
15 lines
172 B
Verilog
`timescale 1ps/1ps
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module top (
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input wire A,
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input wire clk,
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output wire Y
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);
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INVx2_ASAP7_75t_R u_inv (
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.A(A),
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.Y(Y)
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);
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endmodule
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