22 lines
545 B
Verilog
22 lines
545 B
Verilog
module search_latch (clk, in1, in2, out1, out2);
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input clk, in1, in2;
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output out1, out2;
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wire n1, n2, n3, n4, n5;
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// Combinational logic
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AND2_X1 and1 (.A1(in1), .A2(in2), .ZN(n1));
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BUF_X1 buf1 (.A(n1), .Z(n2));
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// Latch: DLH_X1 has D (data) and G (gate/enable)
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DLH_X1 latch1 (.D(n2), .G(clk), .Q(n3));
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// Another latch
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DLH_X1 latch2 (.D(n3), .G(clk), .Q(n4));
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// Regular flip-flop for cross-domain
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DFF_X1 reg1 (.D(n3), .CK(clk), .Q(n5));
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BUF_X1 buf2 (.A(n4), .Z(out1));
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BUF_X1 buf3 (.A(n5), .Z(out2));
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endmodule
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