33 lines
1.9 KiB
Plaintext
33 lines
1.9 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
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create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
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set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
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set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
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set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
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set_disable_timing [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
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set_disable_timing -from {A} [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
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set_disable_timing -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
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set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
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set_disable_timing -from {A2} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
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set_disable_timing [get_ports {in1}]
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set_disable_timing -from {A1} -to {ZN} [get_cells {and1}]
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set_disable_timing -from {A2} -to {ZN} [get_cells {and1}]
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set_disable_timing [get_cells {buf1}]
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set_disable_timing -to {ZN} [get_cells {nand1}]
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set_disable_timing -from {A1} [get_cells {or1}]
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set_disable_timing [get_pins {inv1/A}]
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###############################################################################
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# Environment
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###############################################################################
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###############################################################################
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# Design Rules
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###############################################################################
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