331 lines
11 KiB
Plaintext
331 lines
11 KiB
Plaintext
No differences found.
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Warning 1061: generated clock gclk1 pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 ^ reg2/CK (DFF_X1)
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0.08 5.08 ^ reg2/Q (DFF_X1)
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0.00 5.08 ^ out1 (out)
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5.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-5.08 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Path Group: clk1_2x
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in1 (in)
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0.02 2.02 v buf1/Z (BUF_X1)
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0.05 2.07 v or1/ZN (OR2_X1)
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0.03 2.09 ^ nor1/ZN (NOR2_X1)
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0.00 2.09 ^ reg2/D (DFF_X1)
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2.09 data arrival time
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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5.00 ^ reg2/CK (DFF_X1)
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-0.03 4.97 library setup time
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4.97 data required time
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---------------------------------------------------------
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4.97 data required time
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-2.09 data arrival time
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---------------------------------------------------------
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2.87 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-3.00 17.00 output external delay
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17.00 data required time
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---------------------------------------------------------
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17.00 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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2.00 slack (MET)
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No differences found.
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No differences found.
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No differences found.
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 ^ reg2/CK (DFF_X1)
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0.08 5.08 ^ reg2/Q (DFF_X1)
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0.00 5.08 ^ out1 (out)
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5.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-5.08 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Path Group: clk1_2x
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in1 (in)
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0.02 2.02 v buf1/Z (BUF_X1)
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0.05 2.07 v or1/ZN (OR2_X1)
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0.03 2.09 ^ nor1/ZN (NOR2_X1)
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0.00 2.09 ^ reg2/D (DFF_X1)
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2.09 data arrival time
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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5.00 ^ reg2/CK (DFF_X1)
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-0.03 4.97 library setup time
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4.97 data required time
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---------------------------------------------------------
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4.97 data required time
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-2.09 data arrival time
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---------------------------------------------------------
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2.87 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-3.00 17.00 output external delay
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17.00 data required time
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---------------------------------------------------------
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17.00 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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2.00 slack (MET)
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No differences found.
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No differences found.
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 ^ reg2/CK (DFF_X1)
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0.08 5.08 ^ reg2/Q (DFF_X1)
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0.00 5.08 ^ out1 (out)
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5.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-5.08 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Path Group: clk1_2x
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in1 (in)
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0.02 2.02 v buf1/Z (BUF_X1)
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0.05 2.07 v or1/ZN (OR2_X1)
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0.03 2.09 ^ nor1/ZN (NOR2_X1)
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0.00 2.09 ^ reg2/D (DFF_X1)
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2.09 data arrival time
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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5.00 ^ reg2/CK (DFF_X1)
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-0.03 4.97 library setup time
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4.97 data required time
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---------------------------------------------------------
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4.97 data required time
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-2.09 data arrival time
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---------------------------------------------------------
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2.87 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-3.00 17.00 output external delay
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17.00 data required time
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---------------------------------------------------------
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17.00 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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2.00 slack (MET)
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No differences found.
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No differences found.
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 ^ reg2/CK (DFF_X1)
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0.08 5.08 ^ reg2/Q (DFF_X1)
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0.00 5.08 ^ out1 (out)
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5.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-5.08 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
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Path Group: clk1_2x
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in1 (in)
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0.02 2.02 v buf1/Z (BUF_X1)
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0.05 2.07 v or1/ZN (OR2_X1)
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0.03 2.09 ^ nor1/ZN (NOR2_X1)
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0.00 2.09 ^ reg2/D (DFF_X1)
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2.09 data arrival time
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5.00 5.00 clock clk1_2x (rise edge)
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0.00 5.00 clock network delay (ideal)
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-0.20 4.80 clock uncertainty
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0.00 4.80 clock reconvergence pessimism
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4.80 ^ reg2/CK (DFF_X1)
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-0.03 4.77 library setup time
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4.77 data required time
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---------------------------------------------------------
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4.77 data required time
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-2.09 data arrival time
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---------------------------------------------------------
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2.67 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.08 v reg3/Q (DFF_X1)
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0.00 15.08 v out2 (out)
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15.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (propagated)
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0.00 20.00 clock reconvergence pessimism
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-3.00 17.00 output external delay
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17.00 data required time
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---------------------------------------------------------
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17.00 data required time
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-15.08 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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