44 lines
2.8 KiB
Plaintext
44 lines
2.8 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
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create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
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set_propagated_clock [get_clocks {clk2}]
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create_clock -name vclk1 -period 8.0000
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create_clock -name vclk2 -period 12.0000
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create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
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create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
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create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
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set_clock_uncertainty -setup 0.2000 [get_pins {reg2/CK}]
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
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set_sense -type clock -stop_propagation -clock [get_clocks {clk1}] [get_pins {and1/ZN}]
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set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}]
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set_sense -type clock -negative -clock [get_clocks {clk2}] [get_pins {inv1/ZN}]
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set_clock_groups -name group1 -asynchronous \
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-group [list [get_clocks {clk1}]\
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[get_clocks {gclk1}]]\
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-group [list [get_clocks {clk2}]\
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[get_clocks {gclk2}]]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
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set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
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set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
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set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
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###############################################################################
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# Environment
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###############################################################################
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###############################################################################
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# Design Rules
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###############################################################################
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