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OpenSTA/parasitics/test/parasitics_delete_network.ok

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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
--- Test 1: set then delete manual parasitics ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
75.04 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (propagated)
0.00 500.00 clock reconvergence pessimism
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-5.78 494.22 library setup time
494.22 data required time
---------------------------------------------------------
494.22 data required time
-75.04 data arrival time
---------------------------------------------------------
419.17 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
75.04 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (propagated)
0.00 500.00 clock reconvergence pessimism
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-5.78 494.22 library setup time
494.22 data required time
---------------------------------------------------------
494.22 data required time
-75.04 data arrival time
---------------------------------------------------------
419.17 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
---------------------------------------------------------
503.46 data required time
-201.72 data arrival time
---------------------------------------------------------
301.74 slack (MET)
--- Test 2: SPEF re-read ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Slew Delay Time Description
-----------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
0.00 500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
-----------------------------------------------------------------------
503.46 data required time
-201.72 data arrival time
-----------------------------------------------------------------------
301.74 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
55.73 55.73 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
30.36 86.09 ^ u1/Y (BUFx2_ASAP7_75t_R)
42.76 128.85 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.00 128.85 ^ r3/D (DFFHQx4_ASAP7_75t_R)
128.85 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (propagated)
0.00 500.00 clock reconvergence pessimism
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-10.53 489.47 library setup time
489.47 data required time
---------------------------------------------------------
489.47 data required time
-128.85 data arrival time
---------------------------------------------------------
360.62 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
---------------------------------------------------------
503.46 data required time
-201.72 data arrival time
---------------------------------------------------------
301.74 slack (MET)
--- Test 3: query parasitic state ---
u1/Y rise max pi: 6.699999696078941e-15 2420.0 7.265281956505675e-15
u1/Y fall max pi: 6.699999696078941e-15 2420.0 7.265708014078144e-15
r1/Q rise max pi: 6.699999696078941e-15 2420.0 7.222564390909746e-15
elmore u1/Y->u2/A: 0.0
elmore u1/Y->u2/A min: 0.0
elmore u1/Y->u2/A fall: 0.0
elmore r3/Q->u1/A (should be empty): 0.0
--- Test 4: manual -> SPEF -> manual ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
34.88 110.50 ^ u1/Y (BUFx2_ASAP7_75t_R)
32.94 143.44 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.75 159.19 ^ r3/D (DFFHQx4_ASAP7_75t_R)
159.19 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.43 503.49 library setup time
503.49 data required time
---------------------------------------------------------
503.49 data required time
-159.19 data arrival time
---------------------------------------------------------
344.30 slack (MET)
u1/Y pi after re-set: 9.99999983775159e-18 20000.0 8.00000036650964e-18
elmore u1/Y->u2/A after re-set: 9.9999998245167e-15
--- Test 5: annotation reports ---
Found 0 unannotated drivers.
Found 0 partially unannotated drivers.
Found 0 unannotated drivers.
Found 0 partially unannotated drivers.
--- Test 6: report_net ---
Net r1q
Pin capacitance: 0.399352-0.522565
Wire capacitance: 13.399999-13.400000
Total capacitance: 13.799351-13.922565
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
r1/Q output (DFFHQx4_ASAP7_75t_R)
Load pins
u2/A input (AND2x2_ASAP7_75t_R) 0.399352-0.522565
Net r2q
Pin capacitance: 0.441381-0.577042
Wire capacitance: 13.400000-13.400001
Total capacitance: 13.841380-13.977042
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
r2/Q output (DFFHQx4_ASAP7_75t_R)
Load pins
u1/A input (BUFx2_ASAP7_75t_R) 0.441381-0.577042
Net u1z
Pin capacitance: 0.317075-0.565708
Wire capacitance: 0.000000
Total capacitance: 0.317075-0.565708
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
u1/Y output (BUFx2_ASAP7_75t_R)
Load pins
u2/B input (AND2x2_ASAP7_75t_R) 0.317075-0.565708
Net u2z
Pin capacitance: 0.547946-0.621217
Wire capacitance: 13.400000-13.399999
Total capacitance: 13.947945-14.021215
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
u2/Y output (AND2x2_ASAP7_75t_R)
Load pins
r3/D input (DFFHQx4_ASAP7_75t_R) 0.547946-0.621217
Net out
Pin capacitance: 0.000000
Wire capacitance: 13.400000
Total capacitance: 13.400000
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
r3/Q output (DFFHQx4_ASAP7_75t_R)
Load pins
out output port
Net in1
Pin capacitance: 0.547946-0.621217
Wire capacitance: 13.400000-13.399999
Total capacitance: 13.947945-14.021215
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
in1 input port
Load pins
r1/D input (DFFHQx4_ASAP7_75t_R) 0.547946-0.621217
Net in2
Pin capacitance: 0.547946-0.621217
Wire capacitance: 13.400000-13.399999
Total capacitance: 13.947945-14.021215
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
in2 input port
Load pins
r2/D input (DFFHQx4_ASAP7_75t_R) 0.547946-0.621217
Net clk1
Pin capacitance: 0.405426-0.522765
Wire capacitance: 13.400000
Total capacitance: 13.805426-13.922765
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
clk1 input port
Load pins
r1/CLK input (DFFHQx4_ASAP7_75t_R) 0.405426-0.522765
Net clk2
Pin capacitance: 0.405426-0.522765
Wire capacitance: 13.400000
Total capacitance: 13.805426-13.922765
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
clk2 input port
Load pins
r2/CLK input (DFFHQx4_ASAP7_75t_R) 0.405426-0.522765
Net clk3
Pin capacitance: 0.405426-0.522765
Wire capacitance: 13.400000
Total capacitance: 13.805426-13.922765
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
clk3 input port
Load pins
r3/CLK input (DFFHQx4_ASAP7_75t_R) 0.405426-0.522765
--- Test 7: dcalc reports ---
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
Cell: BUFx2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
A ^ -> Y ^
P = 1.000000 V = 0.770000 T = 0.000000
------- input_net_transition = 50.730160
| total_output_net_capacitance = 0.565282
| 1.440000 2.880000
v --------------------
40.000000 | 20.817699 23.184000
80.000000 | 25.603901 28.101500
Table value = 20.642830
PVT scale factor = 1.000000
Delay = 20.642830
------- input_net_transition = 50.730160
| total_output_net_capacitance = 0.565282
| 1.440000 2.880000
v --------------------
40.000000 | 8.695190 12.602300
80.000000 | 9.942970 13.663500
Table value = 6.686969
PVT scale factor = 1.000000
Slew = 6.686969
Driver waveform slew = 6.686969
.............................................
A v -> Y v
P = 1.000000 V = 0.770000 T = 0.000000
------- input_net_transition = 48.754658
| total_output_net_capacitance = 0.565708
| 1.440000 2.880000
v --------------------
40.000000 | 22.913099 25.263300
80.000000 | 29.534101 32.067902
Table value = 22.910896
PVT scale factor = 1.000000
Delay = 22.910896
------- input_net_transition = 48.754658
| total_output_net_capacitance = 0.565708
| 1.440000 2.880000
v --------------------
40.000000 | 8.298110 11.603800
80.000000 | 9.684140 12.917200
Table value = 6.604076
PVT scale factor = 1.000000
Slew = 6.604076
Driver waveform slew = 6.604076
.............................................
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
Cell: AND2x2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
A ^ -> Y ^
Pi model C2=6.7000 Rpi=2.4200 C1=7.3212, Ceff=10.8977
P = 1.0000 V = 0.7000 T = 25.0000
------- input_net_transition = 50.4065
| total_output_net_capacitance = 10.8977
| 5.7600 11.5200
v --------------------
40.0000 | 31.2805 40.4816
80.0000 | 36.2962 45.4684
Table value = 40.7857
PVT scale factor = 1.0000
Delay = 40.7857
------- input_net_transition = 50.4065
| total_output_net_capacitance = 10.8977
| 5.7600 11.5200
v --------------------
40.0000 | 24.5231 43.6777
80.0000 | 25.2874 44.4204
Table value = 41.8021
PVT scale factor = 1.0000
Slew = 41.8021
Driver waveform slew = 55.9038
.............................................
A v -> Y v
Pi model C2=6.7000 Rpi=2.4200 C1=7.3192, Ceff=10.3510
P = 1.0000 V = 0.7000 T = 25.0000
------- input_net_transition = 48.3599
| total_output_net_capacitance = 10.3510
| 5.7600 11.5200
v --------------------
40.0000 | 35.3497 43.0892
80.0000 | 44.7307 52.6502
Table value = 43.5091
PVT scale factor = 1.0000
Delay = 43.5091
------- input_net_transition = 48.3599
| total_output_net_capacitance = 10.3510
| 5.7600 11.5200
v --------------------
40.0000 | 20.0873 35.0806
80.0000 | 21.4481 36.0591
Table value = 32.2585
PVT scale factor = 1.0000
Slew = 32.2585
Driver waveform slew = 45.5727
.............................................
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
Pi model C2=6.70 Rpi=2.42 C1=7.22, Ceff=9.22
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.22
| 5.76 11.52
v --------------------
40.00 | 59.92 64.09
80.00 | 65.10 69.26
Table value = 63.51
PVT scale factor = 1.00
Delay = 63.51
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.22
| 5.76 11.52
v --------------------
40.00 | 13.01 21.04
80.00 | 13.01 21.05
Table value = 17.83
PVT scale factor = 1.00
Slew = 17.83
Driver waveform slew = 22.83
.............................................
CLK ^ -> Q v
Pi model C2=6.70 Rpi=2.42 C1=7.21, Ceff=8.89
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.89
| 5.76 11.52
v --------------------
40.00 | 57.80 61.63
80.00 | 62.64 66.47
Table value = 60.90
PVT scale factor = 1.00
Delay = 60.90
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.89
| 5.76 11.52
v --------------------
40.00 | 11.30 17.99
80.00 | 11.31 17.98
Table value = 14.94
PVT scale factor = 1.00
Slew = 14.94
Driver waveform slew = 19.18
.............................................
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
Pi model C2=6.70 Rpi=2.42 C1=7.28, Ceff=9.22
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.22
| 5.76 11.52
v --------------------
40.00 | 59.92 64.09
80.00 | 65.10 69.26
Table value = 63.51
PVT scale factor = 1.00
Delay = 63.51
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.22
| 5.76 11.52
v --------------------
40.00 | 13.01 21.04
80.00 | 13.01 21.05
Table value = 17.84
PVT scale factor = 1.00
Slew = 17.84
Driver waveform slew = 22.89
.............................................
CLK ^ -> Q v
Pi model C2=6.70 Rpi=2.42 C1=7.28, Ceff=8.90
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.90
| 5.76 11.52
v --------------------
40.00 | 57.80 61.63
80.00 | 62.64 66.47
Table value = 60.90
PVT scale factor = 1.00
Delay = 60.90
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.90
| 5.76 11.52
v --------------------
40.00 | 11.30 17.99
80.00 | 11.31 17.98
Table value = 14.94
PVT scale factor = 1.00
Slew = 14.94
Driver waveform slew = 19.24
.............................................
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=9.16
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.16
| 5.76 11.52
v --------------------
40.00 | 59.92 64.09
80.00 | 65.10 69.26
Table value = 63.46
PVT scale factor = 1.00
Delay = 63.46
------- input_net_transition = 48.38
| total_output_net_capacitance = 9.16
| 5.76 11.52
v --------------------
40.00 | 13.01 21.04
80.00 | 13.01 21.05
Table value = 17.74
PVT scale factor = 1.00
Slew = 17.74
Driver waveform slew = 22.31
.............................................
CLK ^ -> Q v
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=8.85
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.85
| 5.76 11.52
v --------------------
40.00 | 57.80 61.63
80.00 | 62.64 66.47
Table value = 60.87
PVT scale factor = 1.00
Delay = 60.87
------- input_net_transition = 48.38
| total_output_net_capacitance = 8.85
| 5.76 11.52
v --------------------
40.00 | 11.30 17.99
80.00 | 11.31 17.98
Table value = 14.89
PVT scale factor = 1.00
Slew = 14.89
Driver waveform slew = 18.76
.............................................
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
---------------------------------------------------------
503.46 data required time
-201.72 data arrival time
---------------------------------------------------------
301.74 slack (MET)
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