386 lines
12 KiB
C++
386 lines
12 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#include "Crpr.hh"
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#include <cmath> // abs
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#include <stdio.h>
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#include "Debug.hh"
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#include "Vector.hh"
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#include "Network.hh"
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#include "Graph.hh"
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#include "Sdc.hh"
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#include "Path.hh"
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#include "PathAnalysisPt.hh"
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#include "ClkInfo.hh"
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#include "Tag.hh"
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#include "TagGroup.hh"
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#include "VisitPathEnds.hh"
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#include "PathEnd.hh"
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#include "Search.hh"
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#include "Genclks.hh"
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#include "Variables.hh"
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namespace sta {
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using std::min;
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using std::abs;
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CheckCrpr::CheckCrpr(StaState *sta) :
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StaState(sta)
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{
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}
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// Find the maximum possible crpr (clock min/max delta delay) for a
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// path from it's ClkInfo.
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Arrival
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CheckCrpr::maxCrpr(ClkInfo *clk_info)
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{
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const Path *crpr_clk_path = clk_info->crprClkPath(this);
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if (crpr_clk_path) {
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Arrival other_arrival = otherMinMaxArrival(crpr_clk_path);
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float crpr_diff = abs(delayAsFloat(crpr_clk_path->arrival(),
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EarlyLate::late(),
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this)
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- delayAsFloat(other_arrival, EarlyLate::early(),
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this));
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return crpr_diff;
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}
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return 0.0F;
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}
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Arrival
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CheckCrpr::otherMinMaxArrival(const Path *path)
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{
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PathAnalysisPt *other_ap = path->pathAnalysisPt(this)->tgtClkAnalysisPt();
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Tag *tag = path->tag(this);
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VertexPathIterator other_iter(path->vertex(this),
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path->transition(this),
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other_ap, this);
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while (other_iter.hasNext()) {
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Path *other = other_iter.next();
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if (tagMatchCrpr(other->tag(this), tag))
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return other->arrival();
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}
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// No corresponding path found.
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// Match the arrival so the difference is zero.
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return path->arrival();
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}
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Crpr
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CheckCrpr::checkCrpr(const Path *src_path,
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const Path *tgt_clk_path)
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{
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Crpr crpr;
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Pin *crpr_pin;
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checkCrpr(src_path, tgt_clk_path, crpr, crpr_pin);
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return crpr;
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}
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void
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CheckCrpr::checkCrpr(const Path *src_path,
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const Path *tgt_clk_path,
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// Return values.
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Crpr &crpr,
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Pin *&crpr_pin)
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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if (sdc_->crprActive()
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&& src_path && tgt_clk_path) {
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bool same_pin = (variables_->crprMode() == CrprMode::same_pin);
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checkCrpr1(src_path, tgt_clk_path, same_pin, crpr, crpr_pin);
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}
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}
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void
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CheckCrpr::checkCrpr1(const Path *src_path,
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const Path *tgt_clk_path,
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bool same_pin,
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// Return values.
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Crpr &crpr,
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Pin *&crpr_pin)
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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const Tag *src_tag = src_path->tag(this);
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ClkInfo *src_clk_info = src_tag->clkInfo();
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ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
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const Clock *src_clk = src_clk_info->clock();
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const Clock *tgt_clk = tgt_clk_info->clock();
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const Path *src_clk_path = nullptr;
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if (src_tag->isClock())
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src_clk_path = src_path;
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else
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src_clk_path = src_clk_info->crprClkPath(this);
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const MinMax *src_clk_min_max =
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src_clk_path ? src_clk_path->minMax(this) : src_path->minMax(this);
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if (src_clk && tgt_clk
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&& crprPossible(src_clk, tgt_clk)
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&& src_clk_info->isPropagated()
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&& tgt_clk_info->isPropagated()
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// Note that crpr clk min/max is NOT the same as the path min max.
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// For path from latches that are borrowing the enable path
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// is from the opposite min/max of the data.
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&& src_clk_min_max != tgt_clk_path->minMax(this)
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&& (src_clk_path
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|| src_clk->isGenerated())) {
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// Src path from input port clk path can only be from generated clk path.
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if (src_clk_path == nullptr) {
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src_clk_path = portClkPath(src_clk_info->clkEdge(),
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src_clk_info->clkSrc(),
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src_path->pathAnalysisPt(this));
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}
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findCrpr(src_clk_path, tgt_clk_path, same_pin, crpr, crpr_pin);
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}
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}
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// Find the clk path for an input/output port.
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Path *
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CheckCrpr::portClkPath(const ClockEdge *clk_edge,
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const Pin *clk_src_pin,
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const PathAnalysisPt *path_ap)
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{
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Vertex *clk_vertex = graph_->pinDrvrVertex(clk_src_pin);
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VertexPathIterator path_iter(clk_vertex, clk_edge->transition(),
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path_ap, this);
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while (path_iter.hasNext()) {
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Path *path = path_iter.next();
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if (path->clkEdge(this) == clk_edge
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&& path->isClock(this)) {
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return path;
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}
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}
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return nullptr;
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}
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void
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CheckCrpr::findCrpr(const Path *src_clk_path,
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const Path *tgt_clk_path,
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bool same_pin,
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// Return values.
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Crpr &crpr,
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Pin *&crpr_pin)
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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const Path *src_clk_path1 = src_clk_path;
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const Path *tgt_clk_path1 = tgt_clk_path;
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if (src_clk_path1->clkInfo(this)->clkSrc()
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!= tgt_clk_path1->clkInfo(this)->clkSrc()) {
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// Push src/tgt genclk src paths into a vector,
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// The last genclk src path is at index 0.
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ConstPathSeq src_gclk_paths = genClkSrcPaths(src_clk_path1);
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ConstPathSeq tgt_gclk_paths = genClkSrcPaths(tgt_clk_path1);
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// Search from the first gen clk toward the end
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// of the path to find a common root pin.
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int i = src_gclk_paths.size() - 1;
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int j = tgt_gclk_paths.size() - 1;
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for (; i >= 0 && j >= 0; i--, j--) {
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const Path *src_path = src_gclk_paths[i];
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const Path *tgt_path = tgt_gclk_paths[j];
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if (src_path->clkInfo(this)->clkSrc()
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== tgt_path->clkInfo(this)->clkSrc()) {
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src_clk_path1 = src_gclk_paths[i];
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tgt_clk_path1 = tgt_gclk_paths[j];
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}
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else
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break;
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}
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}
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const Path *src_clk_path2 = src_clk_path1;
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const Path *tgt_clk_path2 = tgt_clk_path1;
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// src_clk_path2 and tgt_clk_path2 are now in the same (gen)clk src path.
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// Use the vertex levels to back up the deeper path to see if they
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// overlap.
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int src_level = src_clk_path2->vertex(this)->level();
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int tgt_level = tgt_clk_path2->vertex(this)->level();
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while (src_clk_path2->pin(this) != tgt_clk_path2->pin(this)) {
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int level_diff = src_level - tgt_level;
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if (level_diff >= 0) {
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src_clk_path2 = src_clk_path2->prevPath();
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if (src_clk_path2 == nullptr)
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break;
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src_level = src_clk_path2->vertex(this)->level();
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}
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if (level_diff <= 0) {
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tgt_clk_path2 = tgt_clk_path2->prevPath();
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if (tgt_clk_path2 == nullptr)
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break;
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tgt_level = tgt_clk_path2->vertex(this)->level();
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}
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}
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if (src_clk_path2 && tgt_clk_path2
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&& (src_clk_path2->transition(this) == tgt_clk_path2->transition(this)
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|| same_pin)) {
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debugPrint(debug_, "crpr", 2, "crpr pin %s",
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network_->pathName(src_clk_path2->pin(this)));
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crpr = findCrpr1(src_clk_path2, tgt_clk_path2);
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crpr_pin = src_clk_path2->pin(this);
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}
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}
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ConstPathSeq
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CheckCrpr::genClkSrcPaths(const Path *path)
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{
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ConstPathSeq gclk_paths;
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ClkInfo *clk_info = path->clkInfo(this);
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const ClockEdge *clk_edge = clk_info->clkEdge();
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const Pin *clk_src = clk_info->clkSrc();
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PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
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gclk_paths.push_back(path);
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Genclks *genclks = search_->genclks();
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while (clk_edge->clock()->isGenerated()) {
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Path *genclk_path = genclks->srcPath(clk_edge, clk_src, path_ap);
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if (genclk_path == nullptr)
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break;
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clk_info = genclk_path->clkInfo(this);
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clk_src = clk_info->clkSrc();
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clk_edge = clk_info->clkEdge();
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gclk_paths.push_back(genclk_path);
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}
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return gclk_paths;
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}
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Crpr
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CheckCrpr::findCrpr1(const Path *src_clk_path,
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const Path *tgt_clk_path)
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{
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if (variables_->pocvEnabled()) {
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// Remove variation on the common path.
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// Note that the crpr sigma is negative to offset the
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// sigma of the common clock path.
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const EarlyLate *src_el = src_clk_path->minMax(this);
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const EarlyLate *tgt_el = tgt_clk_path->minMax(this);
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Arrival src_arrival = src_clk_path->arrival();
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Arrival tgt_arrival = tgt_clk_path->arrival();
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float src_clk_time = src_clk_path->clkEdge(this)->time();
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float tgt_clk_time = tgt_clk_path->clkEdge(this)->time();
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float crpr_mean = abs(delayAsFloat(src_arrival) - src_clk_time
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- (delayAsFloat(tgt_arrival) - tgt_clk_time));
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// Remove the sigma from both source and target path arrivals.
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float crpr_sigma2 = delaySigma2(src_arrival, src_el)
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+ delaySigma2(tgt_arrival, tgt_el);
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return makeDelay2(crpr_mean, -crpr_sigma2, -crpr_sigma2);
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}
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else {
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// The source and target edges are different so the crpr
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// is the min of the source and target max-min delay.
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float src_delta = crprArrivalDiff(src_clk_path);
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float tgt_delta = crprArrivalDiff(tgt_clk_path);
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debugPrint(debug_, "crpr", 2, " src delta %s",
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delayAsString(src_delta, this));
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debugPrint(debug_, "crpr", 2, " tgt delta %s",
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delayAsString(tgt_delta, this));
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float common_delay = min(src_delta, tgt_delta);
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debugPrint(debug_, "crpr", 2, " %s delta %s",
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network_->pathName(src_clk_path->pin(this)),
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delayAsString(common_delay, this));
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return common_delay;
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}
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}
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float
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CheckCrpr::crprArrivalDiff(const Path *path)
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{
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Arrival other_arrival = otherMinMaxArrival(path);
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float crpr_diff = abs(delayAsFloat(path->arrival())
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- delayAsFloat(other_arrival));
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return crpr_diff;
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}
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Crpr
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CheckCrpr::outputDelayCrpr(const Path *src_clk_path,
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const ClockEdge *tgt_clk_edge)
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{
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Crpr crpr;
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Pin *crpr_pin;
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outputDelayCrpr(src_clk_path, tgt_clk_edge, crpr, crpr_pin);
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return crpr;
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}
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void
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CheckCrpr::outputDelayCrpr(const Path *src_path,
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const ClockEdge *tgt_clk_edge,
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// Return values.
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Crpr &crpr,
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Pin *&crpr_pin)
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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if (sdc_->crprActive()) {
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const PathAnalysisPt *path_ap = src_path->pathAnalysisPt(this);
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const PathAnalysisPt *tgt_path_ap = path_ap->tgtClkAnalysisPt();
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bool same_pin = (variables_->crprMode() == CrprMode::same_pin);
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outputDelayCrpr1(src_path,tgt_clk_edge,tgt_path_ap, same_pin,
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crpr, crpr_pin);
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}
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}
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void
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CheckCrpr::outputDelayCrpr1(const Path *src_path,
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const ClockEdge *tgt_clk_edge,
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const PathAnalysisPt *tgt_path_ap,
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bool same_pin,
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// Return values.
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Crpr &crpr,
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Pin *&crpr_pin)
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
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const Clock *tgt_clk = tgt_clk_edge->clock();
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const Clock *src_clk = src_path->clock(this);
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if (src_clk && tgt_clk
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&& src_clk_info->isPropagated()
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&& tgt_clk->isGenerated()
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&& tgt_clk->isPropagated()
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&& crprPossible(src_clk, tgt_clk)) {
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Path *tgt_genclk_path = portClkPath(tgt_clk_edge,
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tgt_clk_edge->clock()->defaultPin(),
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tgt_path_ap);
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Path *src_clk_path = src_path->clkInfo(this)->crprClkPath(this);
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if (src_clk_path)
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findCrpr(src_clk_path, tgt_genclk_path, same_pin, crpr, crpr_pin);
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}
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}
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bool
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CheckCrpr::crprPossible(const Clock *clk1,
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const Clock *clk2)
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{
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return clk1 && clk2
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&& !clk1->isVirtual()
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&& !clk2->isVirtual()
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// Generated clocks can have crpr in the source path.
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&& (clk1 == clk2
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|| clk1->isGenerated()
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|| clk2->isGenerated()
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// Different non-generated clocks with the same source pins (using -add).
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|| PinSet::intersects(&clk1->pins(), &clk2->pins(), network_));
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}
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} // namespace
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