48 lines
880 B
Plaintext
48 lines
880 B
Plaintext
module verilog_bus_test (clk,
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data_in,
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data_out,
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sel,
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enable);
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input clk;
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input [3:0] data_in;
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output [3:0] data_out;
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input sel;
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input enable;
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wire [3:0] n1;
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wire [3:0] n2;
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AND2_X1 and0 (.A1(n1[0]),
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.A2(enable),
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.ZN(n2[0]));
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AND2_X1 and1 (.A1(n1[1]),
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.A2(enable),
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.ZN(n2[1]));
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AND2_X1 and2 (.A1(n1[2]),
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.A2(enable),
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.ZN(n2[2]));
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AND2_X1 and3 (.A1(n1[3]),
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.A2(enable),
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.ZN(n2[3]));
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BUF_X1 buf0 (.A(data_in[0]),
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.Z(n1[0]));
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BUF_X1 buf1 (.A(data_in[1]),
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.Z(n1[1]));
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BUF_X1 buf2 (.A(data_in[2]),
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.Z(n1[2]));
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BUF_X1 buf3 (.A(data_in[3]),
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.Z(n1[3]));
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DFF_X1 reg0 (.D(n2[0]),
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.CK(clk),
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.Q(data_out[0]));
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DFF_X1 reg1 (.D(n2[1]),
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.CK(clk),
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.Q(data_out[1]));
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DFF_X1 reg2 (.D(n2[2]),
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.CK(clk),
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.Q(data_out[2]));
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DFF_X1 reg3 (.D(n2[3]),
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.CK(clk),
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.Q(data_out[3]));
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endmodule
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