119 lines
3.9 KiB
Tcl
119 lines
3.9 KiB
Tcl
# Test verilog read/write with bus ports
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# Targets: VerilogReader.cc (bus port paths, bit select parsing)
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# VerilogWriter.cc (writeInstBusPin, writeInstBusPinBit, bus wire dcls)
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# VerilogLex.ll (bus index lexing)
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# VerilogParse.yy (bus port/wire parsing)
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# Also targets: ConcreteNetwork.cc (bus port operations, findBusBit, fromIndex, toIndex, etc.)
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read verilog with bus ports
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#---------------------------------------------------------------
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puts "--- read verilog with bus ports ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_bus_test.v
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link_design verilog_bus_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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if { [llength $cells] != 12 } {
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puts "WARN: expected 12 cells"
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}
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Query bus ports
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puts "--- bus port queries ---"
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set din_ports [get_ports data_in*]
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puts "data_in* ports: [llength $din_ports]"
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set dout_ports [get_ports data_out*]
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puts "data_out* ports: [llength $dout_ports]"
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# Query individual bus bits
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foreach i {0 1 2 3} {
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set p [get_ports "data_in\[$i\]"]
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puts "data_in\[$i\] dir=[get_property $p direction]"
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}
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foreach i {0 1 2 3} {
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set p [get_ports "data_out\[$i\]"]
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puts "data_out\[$i\] dir=[get_property $p direction]"
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}
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#---------------------------------------------------------------
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# Set up timing constraints
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#---------------------------------------------------------------
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_in[0] data_in[1] data_in[2] data_in[3]}]
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set_input_delay -clock clk 0 [get_ports enable]
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set_input_delay -clock clk 0 [get_ports sel]
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set_output_delay -clock clk 0 [get_ports {data_out[0] data_out[1] data_out[2] data_out[3]}]
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report_checks
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report_checks -path_delay min
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#---------------------------------------------------------------
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# Test get_pins with bus-style patterns
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#---------------------------------------------------------------
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puts "--- pin queries with bus patterns ---"
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set all_pins [get_pins */*]
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puts "all pins: [llength $all_pins]"
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set buf_pins [get_pins buf*/*]
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puts "buf* pins: [llength $buf_pins]"
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set and_pins [get_pins and*/*]
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puts "and* pins: [llength $and_pins]"
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set reg_pins [get_pins reg*/*]
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puts "reg* pins: [llength $reg_pins]"
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#---------------------------------------------------------------
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# Test write_verilog with bus ports
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#---------------------------------------------------------------
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puts "--- write_verilog with bus ports ---"
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set outfile [make_result_file verilog_bus_out.v]
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write_verilog $outfile
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diff_files verilog_bus_out.vok $outfile
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# Write with pwr_gnd to exercise pwr/gnd port direction paths
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set outfile2 [make_result_file verilog_bus_pwr.v]
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write_verilog -include_pwr_gnd $outfile2
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#---------------------------------------------------------------
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# Test report_net with bus nets
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#---------------------------------------------------------------
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puts "--- report_net with bus nets ---"
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foreach net_name {n1[0] n1[1] n1[2] n1[3] n2[0] n2[1] n2[2] n2[3]} {
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report_net $net_name
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}
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#---------------------------------------------------------------
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# Test report_instance on cells connected to bus wires
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#---------------------------------------------------------------
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puts "--- report_instance ---"
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foreach inst_name {buf0 buf1 and0 and1 reg0 reg1} {
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report_instance $inst_name
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}
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#---------------------------------------------------------------
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# Test get_fanin/get_fanout
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#---------------------------------------------------------------
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puts "--- fanin/fanout ---"
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set fi [get_fanin -to [get_ports "data_out\[0\]"] -flat]
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puts "fanin to data_out\[0\]: [llength $fi]"
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set fo [get_fanout -from [get_ports "data_in\[0\]"] -flat]
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puts "fanout from data_in\[0\]: [llength $fo]"
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set fi_cells [get_fanin -to [get_ports "data_out\[0\]"] -only_cells]
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puts "fanin cells to data_out\[0\]: [llength $fi_cells]"
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