505 lines
14 KiB
Plaintext
505 lines
14 KiB
Plaintext
--- report_clock_skew -setup (all clocks) ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- report_clock_skew -hold (all clocks) ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- report_clock_skew -clock clk1 -setup ---
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report_clock_skew -clock: skipped (source bug)
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--- report_clock_skew -clock clk2 -setup ---
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report_clock_skew -clock: skipped (source bug)
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--- report_clock_skew -clock clk1 -hold ---
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report_clock_skew -clock: skipped (source bug)
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--- report_clock_skew -clock clk2 -hold ---
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report_clock_skew -clock: skipped (source bug)
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--- report_clock_skew -digits 6 ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- report_clock_skew -include_internal_latency ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- report_clock_skew -hold -include_internal_latency ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- report_clock_latency (all clocks) ---
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Clock clk1
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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Clock clk2
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_latency -clock clk1 ---
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Clock clk1
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_latency -clock clk2 ---
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Clock clk2
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_latency -include_internal_latency ---
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Clock clk1
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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Clock clk2
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg3/CK
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0.00 network latency reg3/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_latency -digits 6 ---
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Clock clk1
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rise -> rise
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg1/CK
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0.000000 network latency reg1/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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fall -> fall
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg1/CK
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0.000000 network latency reg1/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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Clock clk2
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rise -> rise
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg3/CK
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0.000000 network latency reg3/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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fall -> fall
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg3/CK
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0.000000 network latency reg3/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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--- report_clock_min_period (all clocks) ---
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clk1 period_min = 0.00 fmax = inf
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clk2 period_min = 0.00 fmax = inf
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--- report_clock_min_period -clocks clk1 ---
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clk1 period_min = 0.00 fmax = inf
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--- report_clock_min_period -clocks clk2 ---
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clk2 period_min = 0.00 fmax = inf
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--- report_clock_min_period -include_port_paths ---
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clk1 period_min = 2.08 fmax = 480.43
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clk2 period_min = 3.08 fmax = 324.52
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--- find_clk_min_period clk1 ---
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clk1 min_period: 0.0
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clk1 min_period (port): 2.0814878709529694e-9
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--- find_clk_min_period clk2 ---
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clk2 min_period: 0.0
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clk2 min_period (port): 3.0814879536933404e-9
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--- clock latency + uncertainty ---
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock clk2 (rise edge)
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0.50 15.50 clock network delay (ideal)
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2.00 17.50 v input external delay
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0.00 17.50 v in3 (in)
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0.08 17.58 v or1/ZN (OR2_X1)
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0.03 17.61 ^ nor1/ZN (NOR2_X1)
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0.00 17.61 ^ reg2/D (DFF_X1)
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17.61 data arrival time
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20.00 20.00 clock clk1 (rise edge)
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0.30 20.30 clock network delay (ideal)
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0.00 20.30 clock reconvergence pessimism
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20.30 ^ reg2/CK (DFF_X1)
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-0.03 20.27 library setup time
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20.27 data required time
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---------------------------------------------------------
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20.27 data required time
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-17.61 data arrival time
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---------------------------------------------------------
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2.66 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (ideal)
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0.00 10.30 ^ reg1/CK (DFF_X1)
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0.08 10.38 v reg1/Q (DFF_X1)
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0.00 10.38 v reg3/D (DFF_X1)
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10.38 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.50 15.50 clock network delay (ideal)
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-0.20 15.30 inter-clock uncertainty
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0.00 15.30 clock reconvergence pessimism
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15.30 ^ reg3/CK (DFF_X1)
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-0.04 15.26 library setup time
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15.26 data required time
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---------------------------------------------------------
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15.26 data required time
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-10.38 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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Startpoint: in2 (input port clocked by clk1)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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1.00 1.30 ^ input external delay
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0.00 1.30 ^ in2 (in)
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0.00 1.30 v inv1/ZN (INV_X1)
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0.04 1.34 v and1/ZN (AND2_X1)
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0.01 1.35 ^ nand1/ZN (NAND2_X1)
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0.00 1.35 ^ reg1/D (DFF_X1)
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1.35 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 clock reconvergence pessimism
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0.30 ^ reg1/CK (DFF_X1)
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0.01 0.31 library hold time
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0.31 data required time
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---------------------------------------------------------
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0.31 data required time
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-1.35 data arrival time
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---------------------------------------------------------
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1.05 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 ^ reg1/CK (DFF_X1)
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0.08 0.38 v reg1/Q (DFF_X1)
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0.00 0.38 v reg3/D (DFF_X1)
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0.38 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.50 0.50 clock network delay (ideal)
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0.10 0.60 inter-clock uncertainty
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0.00 0.60 clock reconvergence pessimism
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0.60 ^ reg3/CK (DFF_X1)
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0.00 0.60 library hold time
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0.60 data required time
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---------------------------------------------------------
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0.60 data required time
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-0.38 data arrival time
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---------------------------------------------------------
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-0.22 slack (VIOLATED)
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--- clock skew after latency+uncertainty ---
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- clock_groups ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 ^ reg2/CK (DFF_X1)
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0.08 0.38 ^ reg2/Q (DFF_X1)
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0.00 0.38 ^ out1 (out)
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0.38 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (ideal)
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0.00 10.30 clock reconvergence pessimism
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-2.00 8.30 output external delay
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8.30 data required time
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---------------------------------------------------------
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8.30 data required time
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-0.38 data arrival time
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---------------------------------------------------------
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7.92 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.50 0.50 clock network delay (ideal)
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0.00 0.50 ^ reg3/CK (DFF_X1)
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0.08 0.58 ^ reg3/Q (DFF_X1)
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0.00 0.58 ^ out2 (out)
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0.58 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.50 15.50 clock network delay (ideal)
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0.00 15.50 clock reconvergence pessimism
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-3.00 12.50 output external delay
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12.50 data required time
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---------------------------------------------------------
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12.50 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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11.92 slack (MET)
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Clock clk1
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No launch/capture paths found.
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Clock clk2
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No launch/capture paths found.
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--- remove clock_groups ---
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock clk2 (rise edge)
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0.50 15.50 clock network delay (ideal)
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2.00 17.50 v input external delay
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0.00 17.50 v in3 (in)
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0.08 17.58 v or1/ZN (OR2_X1)
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0.03 17.61 ^ nor1/ZN (NOR2_X1)
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0.00 17.61 ^ reg2/D (DFF_X1)
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17.61 data arrival time
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20.00 20.00 clock clk1 (rise edge)
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0.30 20.30 clock network delay (ideal)
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0.00 20.30 clock reconvergence pessimism
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20.30 ^ reg2/CK (DFF_X1)
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-0.03 20.27 library setup time
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20.27 data required time
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---------------------------------------------------------
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20.27 data required time
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-17.61 data arrival time
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---------------------------------------------------------
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2.66 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (ideal)
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0.00 10.30 ^ reg1/CK (DFF_X1)
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0.08 10.38 v reg1/Q (DFF_X1)
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0.00 10.38 v reg3/D (DFF_X1)
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10.38 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.50 15.50 clock network delay (ideal)
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-0.20 15.30 inter-clock uncertainty
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0.00 15.30 clock reconvergence pessimism
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15.30 ^ reg3/CK (DFF_X1)
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-0.04 15.26 library setup time
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15.26 data required time
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---------------------------------------------------------
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15.26 data required time
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-10.38 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- report_min_pulse_width_checks multi-clock ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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--- report_min_pulse_width_checks -verbose multi-clock ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 reg1/CK
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0.30 open edge arrival time
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5.00 5.00 clock clk1 (fall edge)
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0.30 5.30 clock network delay (ideal)
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0.00 5.30 reg1/CK
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0.00 5.30 clock reconvergence pessimism
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5.30 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_clock_properties ---
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Clock Period Waveform
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----------------------------------------------------
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clk1 10.00 0.00 5.00
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clk2 15.00 0.00 7.50
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