143 lines
4.3 KiB
Tcl
143 lines
4.3 KiB
Tcl
# Test comprehensive clock SDC commands for code coverage
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# create_clock with various options
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############################################################
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# Basic clock
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create_clock -name clk1 -period 10 [get_ports clk1]
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# Clock with waveform
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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# Virtual clock (no port)
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create_clock -name vclk -period 5
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# Clock with -add on same port (additional clock definition)
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create_clock -name clk1_fast -period 5 -add [get_ports clk1]
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# Report clock properties
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report_clock_properties
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############################################################
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# create_generated_clock
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############################################################
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create_generated_clock -name gen_clk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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create_generated_clock -name gen_clk_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
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report_clock_properties
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############################################################
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# set_clock_latency
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############################################################
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# Source latency with rise/fall min/max
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
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set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
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# Network latency
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set_clock_latency 0.2 [get_clocks clk2]
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set_clock_latency -rise -max 0.4 [get_clocks clk2]
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set_clock_latency -fall -min 0.1 [get_clocks clk2]
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############################################################
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# set_clock_uncertainty
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############################################################
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# Simple clock uncertainty
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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# Inter-clock uncertainty
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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############################################################
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# set_clock_transition
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############################################################
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set_clock_transition -rise -max 0.15 [get_clocks clk1]
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set_clock_transition -fall -min 0.08 [get_clocks clk1]
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set_clock_transition 0.1 [get_clocks clk2]
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############################################################
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# set_propagated_clock
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############################################################
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set_propagated_clock [get_clocks clk1]
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############################################################
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# set_clock_groups
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############################################################
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set_clock_groups -logically_exclusive -group [get_clocks clk1] -group [get_clocks clk2]
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# Remove and re-add as physically exclusive
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unset_clock_groups -logically_exclusive -all
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set_clock_groups -physically_exclusive -group [get_clocks clk1] -group [get_clocks clk2]
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unset_clock_groups -physically_exclusive -all
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set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]
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unset_clock_groups -asynchronous -all
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############################################################
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# set_clock_sense
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############################################################
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set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
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############################################################
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# report_checks to verify constraint effects
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############################################################
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report_checks -from [get_ports in1] -to [get_ports out1]
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############################################################
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# Unset/cleanup operations
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############################################################
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unset_propagated_clock [get_clocks clk1]
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unset_clock_latency [get_clocks clk1]
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unset_clock_latency [get_clocks clk2]
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unset_clock_latency -source [get_clocks clk1]
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unset_clock_transition [get_clocks clk1]
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unset_clock_uncertainty -setup [get_clocks clk1]
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unset_clock_uncertainty -hold [get_clocks clk1]
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unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
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unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
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# Delete generated clocks
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delete_generated_clock [get_clocks gen_clk_div2]
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delete_generated_clock [get_clocks gen_clk_mul3]
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# Delete regular clocks
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delete_clock [get_clocks vclk]
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report_clock_properties
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