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https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-08-30 17:52:26 +02:00
Akash LevyandCursor
e9c075ab94
* Implement set_path_margin command Adds a new set_path_margin SDC command that applies a signed slack adjustment to the capture-clock side of timing paths. A positive margin tightens the path (harder to meet) and a negative margin loosens it. Supports -setup/-hold/-from/-through/-to scoping, priority/override semantics matching other exceptions, text and JSON report output, and write_sdc serialisation. Adapted from Silimate PR #57; uses upstream/master Mode/Scene and string_view APIs. Test uses unset_path_exceptions in place of the Silimate-only reset_path alias. Co-authored-by: Cursor <[email protected]> * Fix nested delaySum call indentation to match project style. Co-authored-by: Cursor <[email protected]> * Address review: store PathMargin on PathEnd, split tests Keep the path margin exception on PathEndClkConstrained, add PathEnd::hasPathMargin for report gating, and split the monolithic regression into set_path_margin1–6. Rebased onto upstream/master and document the command in ChangeLog. Co-authored-by: Cursor <[email protected]> * Document set_path_margin in OpenSTA.fodt/pdf Add the command reference, index entry, and note that unset_path_exceptions also clears path margin exceptions. Co-authored-by: Cursor <[email protected]> * Drop [[nodiscard]] from PathEnd::hasPathMargin. Co-authored-by: Cursor <[email protected]> --------- Co-authored-by: Cursor <[email protected]>
61 lines
2.1 KiB
Plaintext
61 lines
2.1 KiB
Plaintext
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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-------------------------------------------------------------
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0.0000 0.0000 clock clk (rise edge)
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0.0000 0.0000 clock network delay (ideal)
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0.0000 0.0000 ^ r1/CK (DFF_X1)
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0.0836 0.0836 ^ r1/Q (DFF_X1)
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0.0277 0.1113 ^ u2/ZN (AND2_X1)
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0.0000 0.1113 ^ r3/D (DFF_X1)
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0.1113 data arrival time
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10.0000 10.0000 clock clk (rise edge)
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0.0000 10.0000 clock network delay (ideal)
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-2.0000 8.0000 path margin
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0.0000 8.0000 clock reconvergence pessimism
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8.0000 ^ r3/CK (DFF_X1)
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-0.0311 7.9689 library setup time
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7.9689 data required time
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-------------------------------------------------------------
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7.9689 data required time
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-0.1113 data arrival time
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-------------------------------------------------------------
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7.8576 slack (MET)
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setup_from_r1 -2.000e-09
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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-------------------------------------------------------------
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0.0000 0.0000 clock clk (rise edge)
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0.0000 0.0000 clock network delay (ideal)
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0.0000 0.0000 ^ r2/CK (DFF_X1)
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0.0772 0.0772 v r2/Q (DFF_X1)
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0.0233 0.1006 v u1/Z (BUF_X1)
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0.0273 0.1278 v u2/ZN (AND2_X1)
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0.0000 0.1278 v r3/D (DFF_X1)
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0.1278 data arrival time
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10.0000 10.0000 clock clk (rise edge)
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0.0000 10.0000 clock network delay (ideal)
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0.0000 10.0000 clock reconvergence pessimism
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10.0000 ^ r3/CK (DFF_X1)
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-0.0390 9.9610 library setup time
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9.9610 data required time
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-------------------------------------------------------------
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9.9610 data required time
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-0.1278 data arrival time
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-------------------------------------------------------------
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9.8332 slack (MET)
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setup_from_r2 none
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