OpenSTA/verilog/test
dsengupta0628 3f2c80a830 Merge branch 'master' into sta_update_upstream_lvf_stuff 2026-03-25 19:55:19 +00:00
..
cpp Merge branch 'master' into sta_update_upstream_lvf_stuff 2026-03-25 19:55:19 +00:00
CMakeLists.txt test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
assign_net.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
bus_connect.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
constant_net.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
positional.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
regression test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
save_ok test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bus.ok test: Fix test failures after master merge 2026-03-11 10:16:27 +09:00
verilog_bus.tcl test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bus_out.vok test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bus_test.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00