320 lines
12 KiB
C++
320 lines
12 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2026, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#pragma once
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#include <string>
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#include <string_view>
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#include <vector>
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#include <map>
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#include "Format.hh"
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#include "Report.hh"
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#include "StringUtil.hh"
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#include "NetworkClass.hh"
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namespace sta {
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class VerilogScanner;
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class VerilogParse;
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class Debug;
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class Report;
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class VerilogAttrEntry;
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class VerilogAttrStmt;
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class VerilogReader;
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class VerilogStmt;
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class VerilogNet;
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class VerilogNetScalar;
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class VerilogModule;
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class VerilogInst;
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class VerilogModuleInst;
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class VerilogLibertyInst;
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class VerilogDcl;
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class VerilogDclBus;
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class VerilogDclArg;
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class VerilogAssign;
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class VerilogNetConcat;
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class VerilogNetConstant;
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class VerilogNetBitSelect;
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class VerilogNetPartSelect;
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class StringRegistry;
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class VerilogBindingTbl;
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class VerilogNetNameIterator;
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class VerilogNetPortRef;
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class LibertyCell;
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class VerilogErrorCmp;
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class VerilogError
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{
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public:
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VerilogError(int id,
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std::string_view filename,
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int line,
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std::string_view msg,
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bool warn);
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const char *msg() const { return msg_.c_str(); }
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std::string_view filename() const { return filename_; }
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int id() const { return id_; }
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int line() const { return line_; }
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bool warn() const { return warn_; }
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private:
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int id_;
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std::string filename_;
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int line_;
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std::string msg_;
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bool warn_;
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friend class VerilogErrorCmp;
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};
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using VerilogModuleMap = std::map<Cell*, VerilogModule*>;
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using VerilogStmtSeq = std::vector<VerilogStmt*>;
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using VerilogNetSeq = std::vector<VerilogNet*>;
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using VerilogDclArgSeq = std::vector<VerilogDclArg*>;
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using VerilogAttrStmtSeq = std::vector<VerilogAttrStmt*>;
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using VerilogAttrEntrySeq = std::vector<VerilogAttrEntry*>;
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using VerilogErrorSeq = std::vector<VerilogError*>;
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class VerilogReader
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{
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public:
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VerilogReader(NetworkReader *network);
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~VerilogReader();
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bool read(std::string_view filename);
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void makeModule(std::string &&module_name,
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VerilogNetSeq *ports,
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VerilogStmtSeq *stmts,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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void makeModule(std::string &&module_name,
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VerilogStmtSeq *port_dcls,
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VerilogStmtSeq *stmts,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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VerilogDcl *makeDcl(PortDirection *dir,
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VerilogDclArgSeq *args,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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VerilogDcl *makeDcl(PortDirection *dir,
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VerilogDclArg *arg,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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VerilogDclArg *makeDclArg(std::string &&net_name);
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VerilogDclArg*makeDclArg(VerilogAssign *assign);
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VerilogDclBus *makeDclBus(PortDirection *dir,
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int from_index,
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int to_index,
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VerilogDclArg *arg,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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VerilogDclBus *makeDclBus(PortDirection *dir,
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int from_index,
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int to_index,
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VerilogDclArgSeq *args,
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VerilogAttrStmtSeq *attr_stmts,
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int line);
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VerilogInst *makeModuleInst(std::string &&module_name,
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std::string &&inst_name,
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VerilogNetSeq *pins,
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VerilogAttrStmtSeq *attr_stmts,
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const int line);
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VerilogAssign *makeAssign(VerilogNet *lhs,
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VerilogNet *rhs,
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int line);
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VerilogNetScalar *makeNetScalar(std::string &&name);
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VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string &&port_vname);
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VerilogNetPortRef *makeNetNamedPortRefScalarNet(std::string &&port_name,
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std::string &&net_name);
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VerilogNetPortRef *makeNetNamedPortRefBitSelect(std::string &&port_name,
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std::string &&bus_name,
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int index);
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VerilogNetPortRef *makeNetNamedPortRefScalar(std::string &&port_name,
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VerilogNet *net);
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VerilogNetPortRef *makeNetNamedPortRefBit(std::string &&port_name,
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int index,
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VerilogNet *net);
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VerilogNetPortRef *makeNetNamedPortRefPart(std::string &&port_name,
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int from_index,
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int to_index,
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VerilogNet *net);
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VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets);
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VerilogNetConstant *makeNetConstant(std::string &&constant,
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int line);
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VerilogNetBitSelect *makeNetBitSelect(std::string &&name,
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int index);
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VerilogNetPartSelect *makeNetPartSelect(std::string &&name,
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int from_index,
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int to_index);
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VerilogModule *module(Cell *cell);
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Instance *linkNetwork(std::string_view top_cell_name,
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bool make_black_boxes,
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bool delete_modules);
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std::string_view filename() const { return filename_; }
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void incrLine();
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Report *report() const { return report_; }
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template <typename... Args>
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void error(int id,
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std::string_view filename,
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int line,
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std::string_view fmt,
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Args &&...args)
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{
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report_->fileError(id, filename, line, fmt, std::forward<Args>(args)...);
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}
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template <typename... Args>
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void warn(int id,
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std::string_view filename,
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int line,
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std::string_view fmt,
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Args &&...args)
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{
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report_->fileWarn(id, filename, line, fmt, std::forward<Args>(args)...);
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}
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const std::string &zeroNetName() const { return zero_net_name_; }
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const std::string &oneNetName() const { return one_net_name_; }
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void deleteModules();
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const std::string &constant10Max() const { return constant10_max_; }
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protected:
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void init(std::string_view filename);
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void makeCellPorts(Cell *cell,
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VerilogModule *module,
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VerilogNetSeq *ports);
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Port *makeCellPort(Cell *cell,
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VerilogModule *module,
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const std::string &port_name);
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void makeNamedPortRefCellPorts(Cell *cell,
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VerilogModule *module,
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VerilogNet *mod_port,
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StringSet &port_names);
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void checkModuleDcls(VerilogModule *module,
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std::set<std::string> &port_names);
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void makeModuleInstBody(VerilogModule *module,
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Instance *inst,
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VerilogBindingTbl *bindings,
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bool make_black_boxes);
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void makeModuleInstNetwork(VerilogModuleInst *mod_inst,
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Instance *parent,
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VerilogModule *parent_module,
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VerilogBindingTbl *parent_bindings,
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bool make_black_boxes);
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void makeLibertyInst(VerilogLibertyInst *lib_inst,
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Instance *parent,
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VerilogModule *parent_module,
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VerilogBindingTbl *parent_bindings);
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void bindGlobalNets(VerilogBindingTbl *bindings);
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void makeNamedInstPins1(Cell *cell,
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Instance *inst,
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VerilogModuleInst *mod_inst,
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VerilogBindingTbl *bindings,
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Instance *parent,
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VerilogBindingTbl *parent_bindings,
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bool is_leaf);
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void makeNamedInstPins(Cell *cell,
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Instance *inst,
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VerilogModuleInst *mod_inst,
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VerilogBindingTbl *bindings,
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Instance *parent,
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VerilogModule *parent_module,
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VerilogBindingTbl *parent_bindings,
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bool is_leaf);
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void makeOrderedInstPins(Cell *cell,
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Instance *inst,
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VerilogModuleInst *mod_inst,
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VerilogBindingTbl *bindings,
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Instance *parent,
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VerilogModule *parent_module,
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VerilogBindingTbl *parent_bindings,
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bool is_leaf);
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void mergeAssignNet(VerilogAssign *assign,
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VerilogModule *module,
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Instance *inst,
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VerilogBindingTbl *bindings);
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void makeInstPin(Instance *inst,
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Port *port,
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VerilogNetNameIterator *net_name_iter,
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VerilogBindingTbl *bindings,
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Instance *parent,
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VerilogBindingTbl *parent_bindings,
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bool is_leaf);
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void makeInstPin(Instance *inst,
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Port *port,
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const std::string &net_name,
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VerilogBindingTbl *bindings,
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Instance *parent,
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VerilogBindingTbl *parent_bindings,
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bool is_leaf);
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template <typename... Args>
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void linkWarn(int id,
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std::string_view filename,
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int line,
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std::string_view msg,
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Args &&...args)
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{
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std::string msg_str = sta::formatRuntime(msg, std::forward<Args>(args)...);
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link_errors_.push_back(new VerilogError(id, filename, line, msg_str, true));
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}
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template <typename... Args>
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void linkError(int id,
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std::string_view filename,
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int line,
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std::string_view msg,
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Args &&...args)
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{
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std::string msg_str = sta::formatRuntime(msg, std::forward<Args>(args)...);
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link_errors_.push_back(new VerilogError(id, filename, line, msg_str, false));
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}
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bool reportLinkErrors();
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bool haveLinkErrors();
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Cell *makeBlackBox(VerilogModuleInst *mod_inst,
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VerilogModule *parent_module);
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void makeBlackBoxNamedPorts(Cell *cell,
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VerilogModuleInst *mod_inst,
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VerilogModule *parent_module);
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void makeBlackBoxOrderedPorts(Cell *cell,
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VerilogModuleInst *mod_inst,
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VerilogModule *parent_module);
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bool isBlackBox(Cell *cell);
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bool hasScalarNamedPortRefs(LibertyCell *liberty_cell,
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VerilogNetSeq *pins);
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std::string filename_;
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Report *report_;
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Debug *debug_;
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NetworkReader *network_;
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Library *library_;
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int black_box_index_;
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VerilogModuleMap module_map_;
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VerilogErrorSeq link_errors_;
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const std::string zero_net_name_;
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const std::string one_net_name_;
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std::string constant10_max_;
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ViewType *view_type_;
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};
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} // namespace sta
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