OpenSTA/verilog
Jaehyun Kim 55259b894b test: Add `save_ok` script
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-27 11:12:27 +09:00
..
test test: Add `save_ok` script 2026-02-27 11:12:27 +09:00
Verilog.i rel 3.0 2026-01-13 09:36:45 -07:00
Verilog.tcl rel 3.0 2026-01-13 09:36:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReader.cc rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReaderPvt.hh rel 3.0 2026-01-13 09:36:45 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rel 3.0 2026-01-13 09:36:45 -07:00