12 lines
317 B
Verilog
12 lines
317 B
Verilog
module sdf_test3 (clk, d, en, q, q_inv);
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input clk, d, en;
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output q, q_inv;
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wire n1, n2, n3, n4;
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BUF_X1 buf1 (.A(d), .Z(n1));
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INV_X1 inv1 (.A(n1), .ZN(n2));
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AND2_X1 and1 (.A1(n2), .A2(en), .ZN(n3));
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OR2_X1 or1 (.A1(n1), .A2(n2), .ZN(n4));
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DFF_X1 reg1 (.D(n3), .CK(clk), .Q(q), .QN(q_inv));
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endmodule
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