53 lines
1.7 KiB
Plaintext
53 lines
1.7 KiB
Plaintext
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 ^ reg2/CK (DFF_X1)
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0.08 0.38 ^ reg2/Q (DFF_X1)
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0.00 0.38 ^ out1 (out)
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0.38 data arrival time
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5.00 5.00 clock clk1 (fall edge)
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0.30 5.30 clock network delay (ideal)
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0.00 5.30 clock reconvergence pessimism
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-3.20 2.10 output external delay
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2.10 data required time
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---------------------------------------------------------
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2.10 data required time
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-0.38 data arrival time
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---------------------------------------------------------
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1.72 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.20 0.20 clock network delay (ideal)
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0.00 0.20 ^ reg3/CK (DFF_X1)
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0.08 0.28 ^ reg3/Q (DFF_X1)
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0.00 0.28 ^ out2 (out)
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0.28 data arrival time
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10.00 10.00 clock clk2 (fall edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.80 7.20 output external delay
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7.20 data required time
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---------------------------------------------------------
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7.20 data required time
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-0.28 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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