277 lines
8.8 KiB
Plaintext
277 lines
8.8 KiB
Plaintext
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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--- cell property queries ---
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total cells: 5
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u1: ref=BUFx2_ASAP7_75t_R lib=asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 full=u1
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u2: ref=AND2x2_ASAP7_75t_R lib=asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 full=u2
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r1: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r1
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r2: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r2
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r3: ref=DFFHQx4_ASAP7_75t_R lib=asap7sc7p5t_SEQ_RVT_FF_nldm_220123 full=r3
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--- pin direction / connectivity ---
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u1/A: dir=input net=r2q
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u1/Y: dir=output net=u1z
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u2/A: dir=input net=r1q
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u2/B: dir=input net=u1z
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u2/Y: dir=output net=u2z
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r1/CLK: dir=input net=clk1
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r1/D: dir=input net=in1
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r1/Q: dir=output net=r1q
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--- net queries ---
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total nets: 10
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net r1q: r1q
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net r2q: r2q
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net u1z: u1z
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net u2z: u2z
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net in1: in1
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net in2: in2
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net out: out
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net clk1: clk1
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net clk2: clk2
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net clk3: clk3
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--- report_net for various nets ---
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Net r1q
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Pin capacitance: 0.40-0.52
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Wire capacitance: 0.00
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Total capacitance: 0.40-0.52
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r1/Q output (DFFHQx4_ASAP7_75t_R)
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Load pins
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u2/A input (AND2x2_ASAP7_75t_R) 0.40-0.52
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Net u1z
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Pin capacitance: 0.32-0.57
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Wire capacitance: 0.00
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Total capacitance: 0.32-0.57
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u1/Y output (BUFx2_ASAP7_75t_R)
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Load pins
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u2/B input (AND2x2_ASAP7_75t_R) 0.32-0.57
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Net u2z
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Pin capacitance: 0.55-0.62
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Wire capacitance: 0.00
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Total capacitance: 0.55-0.62
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u2/Y output (AND2x2_ASAP7_75t_R)
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Load pins
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r3/D input (DFFHQx4_ASAP7_75t_R) 0.55-0.62
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--- report_instance ---
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Instance u1
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Cell: BUFx2_ASAP7_75t_R
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Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
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Path cells: BUFx2_ASAP7_75t_R
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Input pins:
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A input r2q
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Output pins:
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Y output u1z
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance u2
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Cell: AND2x2_ASAP7_75t_R
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Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
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Path cells: AND2x2_ASAP7_75t_R
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Input pins:
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A input r1q
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B input u1z
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Output pins:
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Y output u2z
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance r1
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Cell: DFFHQx4_ASAP7_75t_R
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Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
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Path cells: DFFHQx4_ASAP7_75t_R
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Input pins:
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CLK input clk1
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D input in1
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Output pins:
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Q output r1q
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Instance r2
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Cell: DFFHQx4_ASAP7_75t_R
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Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
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Path cells: DFFHQx4_ASAP7_75t_R
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Input pins:
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CLK input clk2
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D input in2
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Output pins:
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Q output r2q
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Instance r3
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Cell: DFFHQx4_ASAP7_75t_R
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Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
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Path cells: DFFHQx4_ASAP7_75t_R
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Input pins:
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CLK input clk3
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D input u2z
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Output pins:
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Q output out
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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--- filter expressions on cells ---
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BUFx* cells: 1
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INVx* cells: 0
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DFFC* cells: 0
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--- pin pattern matching ---
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*/CLK pins: 3
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*/D pins: 3
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*/Q pins: 3
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*/Y pins: 2
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--- hierarchical queries ---
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hierarchical cells: 5
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hierarchical nets: 10
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hierarchical pins: 20
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--- port queries ---
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total ports: 6
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port in1: direction=input
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port in2: direction=input
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port out: direction=output
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port clk1: direction=input
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port clk2: direction=input
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port clk3: direction=input
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--- liberty library queries ---
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libraries count: 5
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lib: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
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lib: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
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lib: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
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lib: asap7sc7p5t_OA_RVT_FF_nldm_211120
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lib: asap7sc7p5t_AO_RVT_FF_nldm_211120
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--- lib cell pattern queries ---
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all lib cells: 202
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BUF* lib cells: 12
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INV* lib cells: 11
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--- collection queries ---
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all_inputs: 5
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all_outputs: 1
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all_clocks: 1
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all_registers: 3
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all_registers -data_pins: 3
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all_registers -clock_pins: 3
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all_registers -output_pins: 3
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--- timing analysis ---
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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45.31 45.31 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R)
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14.88 71.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
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0.00 71.95 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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71.95 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-7.11 492.89 library setup time
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492.89 data required time
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---------------------------------------------------------
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492.89 data required time
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-71.95 data arrival time
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---------------------------------------------------------
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420.94 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.00 1.00 v r1/D (DFFHQx4_ASAP7_75t_R)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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6.33 6.33 library hold time
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6.33 data required time
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---------------------------------------------------------
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6.33 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-5.33 slack (VIOLATED)
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Warning 168: network_properties.tcl line 1, unknown field nets.
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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1 0.58 6.09 45.31 45.31 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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6.09 0.00 45.31 ^ u1/A (BUFx2_ASAP7_75t_R)
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1 0.57 5.15 11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R)
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5.15 0.00 57.08 ^ u2/B (AND2x2_ASAP7_75t_R)
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1 0.62 6.96 14.88 71.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
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6.96 0.00 71.95 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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71.95 data arrival time
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0.00 500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-7.11 492.89 library setup time
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492.89 data required time
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-----------------------------------------------------------------------------
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492.89 data required time
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-71.95 data arrival time
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-----------------------------------------------------------------------------
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420.94 slack (MET)
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