259 lines
9.4 KiB
Tcl
259 lines
9.4 KiB
Tcl
# Test hierarchical network operations for coverage improvement.
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# Targets: ConcreteNetwork.cc (hierarchical instance/pin/net iteration,
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# childIterator, findChild, findNet in child context, instancePinIterator,
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# instanceNetIterator, cellName, portCount, addConstantNet, clearConstantNets,
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# mergeInto path, netMergedInto, makeCloneInstance, setName)
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# Network.cc (findInstanceRelative, pathNameNet, pathNameTerm, pathName for
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# hierarchical pins, connectedNets, highestNetAbove, highestConnectedNet,
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# hierarchyLevel, isInside, isHierarchical, leafInstanceIterator,
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# instanceCount, pinCount, netCount, leafInstanceCount, leafPinCount)
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# SdcNetwork.cc (findPin, findNet across hierarchy, escapeDividers,
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# escapeBrackets, portDirection, makePort, deletePort)
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# HpinDrvrLoad.cc (visitHpinDrvrLoads through hierarchical pin traversal)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog network_hier_test.v
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link_design network_hier_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2}]
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set_input_transition 0.1 [get_ports {in1 in2 in3 clk}]
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#---------------------------------------------------------------
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# Test hierarchical cell queries
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# Exercises: findInstancesMatching with hierarchy, childIterator,
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# isHierarchical, isLeaf, findChild
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#---------------------------------------------------------------
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puts "--- hierarchical cell queries ---"
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set all_cells [get_cells *]
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puts "flat cells: [llength $all_cells]"
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set hier_cells [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier_cells]"
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# Query sub-blocks
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set sub_cells [get_cells sub*]
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puts "sub* cells (flat): [llength $sub_cells]"
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set sub_hier [get_cells -hierarchical sub*]
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puts "sub* cells (hier): [llength $sub_hier]"
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# Query cells inside sub-blocks
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set sub1_cells [get_cells -hierarchical sub1/*]
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puts "sub1/* cells (hier): [llength $sub1_cells]"
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set sub2_cells [get_cells -hierarchical sub2/*]
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puts "sub2/* cells (hier): [llength $sub2_cells]"
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# Query all leaf cells hierarchically
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set leaf_hier [get_cells -hierarchical *gate*]
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puts "*gate* cells (hier): [llength $leaf_hier]"
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#---------------------------------------------------------------
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# Test hierarchical pin queries
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# Exercises: findPinsMatching with hierarchy, hierarchical pin paths,
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# pathName for hierarchical pins
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#---------------------------------------------------------------
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puts "--- hierarchical pin queries ---"
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set all_pins [get_pins */*]
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puts "flat pins: [llength $all_pins]"
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set hier_pins [get_pins -hierarchical *]
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puts "hierarchical all pins: [llength $hier_pins]"
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# Query pins inside sub-blocks
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set sub1_hier_pins [get_pins -hierarchical sub1/*]
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puts "sub1/* pins (hier): [llength $sub1_hier_pins]"
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set sub2_hier_pins [get_pins -hierarchical sub2/*]
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puts "sub2/* pins (hier): [llength $sub2_hier_pins]"
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# Query specific pin paths through hierarchy
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set sub1_and [get_pins sub1/and_gate/A1]
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puts "sub1/and_gate/A1: [get_full_name $sub1_and]"
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# Top-level instance pins (port pins)
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set port_pins_in [get_pins -hierarchical */A]
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puts "*/A pins (hier): [llength $port_pins_in]"
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set port_pins_out [get_pins -hierarchical */Z]
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puts "*/Z pins (hier): [llength $port_pins_out]"
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set port_pins_zn [get_pins -hierarchical */ZN]
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puts "*/ZN pins (hier): [llength $port_pins_zn]"
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#---------------------------------------------------------------
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# Test hierarchical net queries
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# Exercises: findNetsMatching with hierarchy, pathNameNet
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#---------------------------------------------------------------
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puts "--- hierarchical net queries ---"
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set all_nets [get_nets *]
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puts "flat nets: [llength $all_nets]"
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set hier_nets [get_nets -hierarchical *]
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puts "hierarchical nets: [llength $hier_nets]"
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set w_nets [get_nets w*]
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puts "w* nets (flat): [llength $w_nets]"
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set hier_w_nets [get_nets -hierarchical w*]
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puts "w* nets (hier): [llength $hier_w_nets]"
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#---------------------------------------------------------------
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# Test port property queries
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# Exercises: portDirection, isInput, isOutput, isBidirect
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#---------------------------------------------------------------
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puts "--- port properties ---"
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set all_ports [get_ports *]
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puts "total ports: [llength $all_ports]"
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foreach port_name {clk in1 in2 in3 out1 out2} {
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set p [get_ports $port_name]
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set dir [get_property $p direction]
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puts "port $port_name: direction=$dir"
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}
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# Filter ports by direction
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set in_ports [get_ports -filter "direction == input"]
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puts "input ports: [llength $in_ports]"
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set out_ports [get_ports -filter "direction == output"]
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puts "output ports: [llength $out_ports]"
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#---------------------------------------------------------------
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# Test instance properties across hierarchy
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# Exercises: cellName, ref_name, lib_name, is_hierarchical
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#---------------------------------------------------------------
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puts "--- instance properties ---"
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foreach inst_name {buf_in sub1 sub2 inv1 reg1 buf_out1 buf_out2} {
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set inst [get_cells $inst_name]
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set ref [get_property $inst ref_name]
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set full [get_full_name $inst]
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puts "$inst_name: ref=$ref full=$full"
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}
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#---------------------------------------------------------------
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# Test report_instance across hierarchy
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# Exercises: instancePinIterator, portCount for each cell
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#---------------------------------------------------------------
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puts "--- report_instance hierarchy ---"
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foreach inst_name {buf_in sub1 sub2 inv1 reg1 buf_out1 buf_out2} {
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report_instance $inst_name
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puts "report_instance $inst_name: done"
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}
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#---------------------------------------------------------------
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# Test report_net for internal hierarchical nets
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# Exercises: netPinIterator, net driver/load identification
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#---------------------------------------------------------------
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puts "--- report_net internal ---"
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foreach net_name {w1 w2 w3 w4 w5} {
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report_net $net_name
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puts "report_net $net_name: done"
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}
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#---------------------------------------------------------------
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# Test fanin/fanout traversal through hierarchy
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# Exercises: visitDrvrLoadsThruHierPin, HpinDrvrLoad paths
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#---------------------------------------------------------------
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puts "--- fanin/fanout through hierarchy ---"
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set fi_out1 [get_fanin -to [get_ports out1] -flat]
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puts "fanin to out1 flat: [llength $fi_out1]"
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set fi_out1_cells [get_fanin -to [get_ports out1] -only_cells]
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puts "fanin to out1 cells: [llength $fi_out1_cells]"
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set fi_out1_start [get_fanin -to [get_ports out1] -startpoints_only]
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puts "fanin to out1 startpoints: [llength $fi_out1_start]"
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set fo_in1 [get_fanout -from [get_ports in1] -flat]
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puts "fanout from in1 flat: [llength $fo_in1]"
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set fo_in1_cells [get_fanout -from [get_ports in1] -only_cells]
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puts "fanout from in1 cells: [llength $fo_in1_cells]"
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set fo_in1_end [get_fanout -from [get_ports in1] -endpoints_only]
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puts "fanout from in1 endpoints: [llength $fo_in1_end]"
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# Fanin/out with different trace arcs
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set fi_timing [get_fanin -to [get_ports out2] -flat -trace_arcs timing]
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puts "fanin to out2 timing trace: [llength $fi_timing]"
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set fi_all [get_fanin -to [get_ports out2] -flat -trace_arcs all]
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puts "fanin to out2 all trace: [llength $fi_all]"
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set fo_all [get_fanout -from [get_ports in2] -flat -trace_arcs all]
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puts "fanout from in2 all trace: [llength $fo_all]"
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# Fanin/out with levels
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set fi_lev1 [get_fanin -to [get_ports out1] -flat -levels 1]
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puts "fanin to out1 levels=1: [llength $fi_lev1]"
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set fi_lev3 [get_fanin -to [get_ports out1] -flat -levels 3]
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puts "fanin to out1 levels=3: [llength $fi_lev3]"
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set fo_lev1 [get_fanout -from [get_ports in1] -flat -levels 1]
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puts "fanout from in1 levels=1: [llength $fo_lev1]"
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#---------------------------------------------------------------
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# Test timing analysis through hierarchy
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# Exercises: graph construction with hierarchical instances
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#---------------------------------------------------------------
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puts "--- timing through hierarchy ---"
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report_checks
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report_checks -path_delay min
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report_checks -path_delay max
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out1]
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report_checks -from [get_ports in3] -to [get_ports out2]
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -format full_clock
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#---------------------------------------------------------------
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# Test network modification in hierarchical context
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# Exercises: make_instance, connect_pin, disconnect_pin, delete_instance
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# in presence of hierarchical instances
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#---------------------------------------------------------------
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puts "--- network modification with hierarchy ---"
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set new_buf [make_instance new_hier_buf NangateOpenCellLibrary/BUF_X1]
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set new_net [make_net new_hier_net]
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connect_pin new_hier_net new_hier_buf/A
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disconnect_pin new_hier_net new_hier_buf/A
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delete_instance new_hier_buf
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delete_net new_hier_net
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#---------------------------------------------------------------
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# Test all_registers in hierarchical context
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#---------------------------------------------------------------
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puts "--- registers in hierarchy ---"
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set regs [all_registers]
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puts "all_registers: [llength $regs]"
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set reg_data [all_registers -data_pins]
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puts "register data_pins: [llength $reg_data]"
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set reg_clk [all_registers -clock_pins]
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puts "register clock_pins: [llength $reg_clk]"
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set reg_out [all_registers -output_pins]
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puts "register output_pins: [llength $reg_out]"
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#---------------------------------------------------------------
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# Test report_check_types in hierarchical context
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#---------------------------------------------------------------
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puts "--- report_check_types ---"
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report_check_types -max_delay -min_delay -verbose
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