505 lines
14 KiB
Plaintext
505 lines
14 KiB
Plaintext
--- hierarchical cell queries ---
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flat cells: 7
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hierarchical cells: 11
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sub* cells (flat): 2
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sub* cells (hier): 2
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Warning 349: network_hierarchy.tcl line 1, instance 'sub1/*' not found.
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sub1/* cells (hier): 0
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Warning 349: network_hierarchy.tcl line 1, instance 'sub2/*' not found.
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sub2/* cells (hier): 0
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*gate* cells (hier): 4
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--- hierarchical pin queries ---
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flat pins: 20
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hierarchical all pins: 30
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sub1/* pins (hier): 3
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sub2/* pins (hier): 3
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sub1/and_gate/A1: sub1/and_gate/A1
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*/A pins (hier): 8
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*/Z pins (hier): 5
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*/ZN pins (hier): 3
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--- hierarchical net queries ---
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flat nets: 11
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hierarchical nets: 19
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w* nets (flat): 5
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w* nets (hier): 5
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--- port properties ---
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total ports: 6
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port clk: direction=input
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port in1: direction=input
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port in2: direction=input
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port in3: direction=input
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port out1: direction=output
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port out2: direction=output
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input ports: 4
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output ports: 2
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--- instance properties ---
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buf_in: ref=BUF_X1 full=buf_in
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sub1: ref=sub_block full=sub1
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sub2: ref=sub_block full=sub2
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inv1: ref=INV_X1 full=inv1
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reg1: ref=DFF_X1 full=reg1
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buf_out1: ref=BUF_X2 full=buf_out1
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buf_out2: ref=BUF_X1 full=buf_out2
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--- report_instance hierarchy ---
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Instance buf_in
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output w1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf_in: done
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Instance sub1
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Cell: sub_block
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Library: verilog
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Path cells: sub_block
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Input pins:
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A input w1
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B input in2
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Output pins:
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Y output w2
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Children:
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and_gate (AND2_X1)
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buf_gate (BUF_X1)
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report_instance sub1: done
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Instance sub2
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Cell: sub_block
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Library: verilog
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Path cells: sub_block
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Input pins:
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A input w2
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B input in3
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Output pins:
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Y output w3
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Children:
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and_gate (AND2_X1)
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buf_gate (BUF_X1)
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report_instance sub2: done
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input w3
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Output pins:
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ZN output w4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance inv1: done
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input w4
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CK input clk
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Output pins:
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Q output w5
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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report_instance reg1: done
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Instance buf_out1
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Cell: BUF_X2
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Library: NangateOpenCellLibrary
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Path cells: BUF_X2
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Input pins:
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A input w5
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Output pins:
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Z output out1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf_out1: done
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Instance buf_out2
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input w3
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Output pins:
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Z output out2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf_out2: done
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--- report_net internal ---
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Net w1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_in/Z output (BUF_X1)
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Load pins
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sub1/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/A input
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report_net w1: done
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Net w2
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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sub1/buf_gate/Z output (BUF_X1)
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Load pins
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sub2/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/Y output
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sub2/A input
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report_net w2: done
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Net w3
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Pin capacitance: 2.42-2.67
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Wire capacitance: 0.00
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Total capacitance: 2.42-2.67
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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sub2/buf_gate/Z output (BUF_X1)
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Load pins
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buf_out2/A input (BUF_X1) 0.88-0.97
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inv1/A input (INV_X1) 1.55-1.70
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Hierarchical pins
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sub2/Y output
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report_net w3: done
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Net w4
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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report_net w4: done
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Net w5
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Pin capacitance: 1.59-1.78
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Wire capacitance: 0.00
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Total capacitance: 1.59-1.78
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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reg1/Q output (DFF_X1)
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Load pins
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buf_out1/A input (BUF_X2) 1.59-1.78
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report_net w5: done
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--- fanin/fanout through hierarchy ---
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fanin to out1 flat: 5
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fanin to out1 cells: 3
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fanin to out1 startpoints: 1
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fanout from in1 flat: 17
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fanout from in1 cells: 2
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fanout from in1 endpoints: 0
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fanin to out2 timing trace: 18
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fanin to out2 all trace: 18
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fanout from in2 all trace: 15
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fanin to out1 levels=1: 3
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fanin to out1 levels=3: 5
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fanout from in1 levels=1: 3
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--- timing through hierarchy ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in3 (in)
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0.04 0.04 ^ sub2/and_gate/ZN (AND2_X1)
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0.02 0.07 ^ sub2/buf_gate/Z (BUF_X1)
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0.01 0.07 v inv1/ZN (INV_X1)
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0.00 0.07 v reg1/D (DFF_X1)
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0.07 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.07 data arrival time
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---------------------------------------------------------
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0.07 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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No paths found.
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No paths found.
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Startpoint: in3 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.06 0.06 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.09 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.11 v buf_out2/Z (BUF_X1)
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0.00 0.11 v out2 (out)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.89 slack (MET)
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Warning 168: network_hierarchy.tcl line 1, unknown field nets.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.10 0.00 0.00 v in1 (in)
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0.10 0.00 0.00 v buf_in/A (BUF_X1)
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1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1)
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0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1)
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1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1)
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1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1)
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1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1)
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2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.00 0.16 v inv1/A (INV_X1)
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1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1)
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0.01 0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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-----------------------------------------------------------------------------
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9.80 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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--- network modification with hierarchy ---
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--- registers in hierarchy ---
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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--- report_check_types ---
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in3 (in)
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0.04 0.04 ^ sub2/and_gate/ZN (AND2_X1)
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0.02 0.07 ^ sub2/buf_gate/Z (BUF_X1)
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0.01 0.07 v inv1/ZN (INV_X1)
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0.00 0.07 v reg1/D (DFF_X1)
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0.07 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.07 data arrival time
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---------------------------------------------------------
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0.07 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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