177 lines
6.1 KiB
Tcl
177 lines
6.1 KiB
Tcl
# Test bus/bundle name parsing and querying
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# Targets: ParseBus.cc (parseBusName with range, subscript_wild, escapeChars)
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# ConcreteNetwork.cc (makeBusPort, groupBusPorts, isBus, isBundle, busName,
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# findBusBit, fromIndex, toIndex, size, portBitCount, findMember,
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# memberIterator, hasMember)
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# Network.cc (busIndexInRange, hasMember, findPortsMatching)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../verilog/test/verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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#---------------------------------------------------------------
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# Test bus port queries (exercises isBus, fromIndex, toIndex, size)
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#---------------------------------------------------------------
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puts "--- bus port queries ---"
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# Query all ports
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set all_ports [get_ports *]
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puts "total ports: [llength $all_ports]"
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# Query bus ports by pattern
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set data_a_ports [get_ports data_a*]
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puts "data_a* ports: [llength $data_a_ports]"
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set data_b_ports [get_ports data_b*]
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puts "data_b* ports: [llength $data_b_ports]"
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set result_ports [get_ports result*]
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puts "result* ports: [llength $result_ports]"
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#---------------------------------------------------------------
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# Test individual bus bit queries
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# Exercises ParseBus.cc parseBusName variants
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#---------------------------------------------------------------
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puts "--- individual bus bit queries ---"
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foreach i {0 1 2 3 4 5 6 7} {
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set p [get_ports "data_a\[$i\]"]
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set dir [get_property $p direction]
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puts "data_a\[$i\] direction: $dir"
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}
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foreach i {0 1 2 3 4 5 6 7} {
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set p [get_ports "result\[$i\]"]
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set dir [get_property $p direction]
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puts "result\[$i\] direction: $dir"
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}
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#---------------------------------------------------------------
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# Test wildcard bus subscript queries (exercises subscript_wild path)
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#---------------------------------------------------------------
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puts "--- wildcard bus subscript ---"
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set wild_a [get_ports {data_a[*]}]
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puts "data_a\[*\] ports: [llength $wild_a]"
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set wild_b [get_ports {data_b[*]}]
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puts "data_b\[*\] ports: [llength $wild_b]"
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set wild_r [get_ports {result[*]}]
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puts "result\[*\] ports: [llength $wild_r]"
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#---------------------------------------------------------------
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# Test get_pins with bus-style patterns
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# Exercises parseBusName in pin query context
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#---------------------------------------------------------------
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puts "--- bus-style pin queries ---"
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set all_pins [get_pins */*]
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puts "all pins: [llength $all_pins]"
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set buf_a_pins [get_pins buf_a*/*]
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puts "buf_a* pins: [llength $buf_a_pins]"
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set and_pins [get_pins and*/*]
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puts "and* pins: [llength $and_pins]"
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set reg_pins [get_pins reg*/*]
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puts "reg* pins: [llength $reg_pins]"
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#---------------------------------------------------------------
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# Test get_nets with bus patterns
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# Exercises parseBusName in net query context
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#---------------------------------------------------------------
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puts "--- bus-style net queries ---"
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set all_nets [get_nets *]
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puts "all nets: [llength $all_nets]"
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set stage1_nets [get_nets stage1*]
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puts "stage1* nets: [llength $stage1_nets]"
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set stage2_nets [get_nets stage2*]
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puts "stage2* nets: [llength $stage2_nets]"
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#---------------------------------------------------------------
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# Test get_cells with various patterns (exercises findChildrenMatching)
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#---------------------------------------------------------------
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puts "--- cell pattern queries ---"
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set all_cells [get_cells *]
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puts "total cells: [llength $all_cells]"
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set buf_cells [get_cells buf*]
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puts "buf* cells: [llength $buf_cells]"
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set and_cells [get_cells and*]
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puts "and* cells: [llength $and_cells]"
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set reg_cells [get_cells reg*]
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puts "reg* cells: [llength $reg_cells]"
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set or_cells [get_cells or*]
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puts "or* cells: [llength $or_cells]"
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#---------------------------------------------------------------
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# Test hierarchical queries on bus design
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#---------------------------------------------------------------
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puts "--- hierarchical queries ---"
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set hier_cells [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier_cells]"
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set hier_nets [get_nets -hierarchical *]
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puts "hierarchical nets: [llength $hier_nets]"
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set hier_pins [get_pins -hierarchical *]
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puts "hierarchical pins: [llength $hier_pins]"
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#---------------------------------------------------------------
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# Test report_net on bus nets
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#---------------------------------------------------------------
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puts "--- report_net on bus nets ---"
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foreach net {stage1[0] stage1[7] stage2[0] stage2[7]} {
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report_net $net
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puts "report_net $net: done"
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}
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#---------------------------------------------------------------
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# Test report_instance on cells in bus design
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#---------------------------------------------------------------
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puts "--- report_instance on cells ---"
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foreach inst {buf_a0 and0 reg0 or_carry buf_carry} {
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report_instance $inst
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puts "report_instance $inst: done"
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}
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#---------------------------------------------------------------
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# Test get_lib_cells with patterns
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# Exercises findPortsMatching on liberty cells
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#---------------------------------------------------------------
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puts "--- lib cell queries ---"
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set buf_lib [get_lib_cells NangateOpenCellLibrary/BUF*]
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puts "BUF* lib cells: [llength $buf_lib]"
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set and_lib [get_lib_cells NangateOpenCellLibrary/AND*]
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puts "AND* lib cells: [llength $and_lib]"
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set or_lib [get_lib_cells NangateOpenCellLibrary/OR*]
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puts "OR* lib cells: [llength $or_lib]"
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set inv_lib [get_lib_cells NangateOpenCellLibrary/INV*]
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puts "INV* lib cells: [llength $inv_lib]"
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set dff_lib [get_lib_cells NangateOpenCellLibrary/DFF*]
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puts "DFF* lib cells: [llength $dff_lib]"
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#---------------------------------------------------------------
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# Timing checks to exercise bus timing paths
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#---------------------------------------------------------------
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puts "--- timing analysis ---"
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report_checks
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report_checks -path_delay min
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report_checks -from [get_ports {data_a[0]}] -to [get_ports {result[0]}]
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report_checks -fields {slew cap input_pins nets fanout}
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