mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-01 02:17:08 +02:00
Jaehyun Kim
e7b861051d
After merging upstream changes, fix all build errors in C++ test files and regolden Tcl test golden files to match updated code output. Build fixes: - dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use EXPECT_NEAR for uninitialized subnormal float comparison - liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed LibertyBuilder() default constructor in #if 0 - liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder() call to use sta_->debug()/report(); wrap old visitor tests in #if 0 - search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr comparison (now returns std::string&) - search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock tests to expect throw (API now requires linked network) Tcl test fixes: - Remove calls to removed APIs: report_path_end_header/footer, report_path_end2 from 6 search test scripts; regolden their .ok files - Regolden .ok files for liberty (15), graph (1), network (8), parasitics (3), sdc (3), util (2), verilog (8) modules to reflect upstream format changes (timing arcs output, pin ordering, spacing) All 6103 tests now pass. Signed-off-by: Jaehyun Kim <[email protected]>
176 lines
4.4 KiB
Plaintext
176 lines
4.4 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- extensive instance creation ---
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total cells: 15
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test_inst_* cells: 12
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--- connect/disconnect cycle ---
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--- multi-pin connections ---
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Net shared_net1
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Pin capacitance: 2.46-2.75
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Wire capacitance: 0.00
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Total capacitance: 2.46-2.75
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Number of drivers: 0
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Number of loads: 2
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Number of pins: 2
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Load pins
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test_inst_0/A input (BUF_X1) 0.88-0.97
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test_inst_1/A input (BUF_X2) 1.59-1.78
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--- replace_cell tests ---
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buf1 -> BUF_X2: ref=BUF_X2
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buf1 -> BUF_X4: ref=BUF_X4
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buf1 -> BUF_X8: ref=BUF_X8
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buf1 -> BUF_X16: ref=BUF_X16
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- delete test instances ---
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remaining cells: 3
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--- net creation/deletion patterns ---
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total nets with bulk: 26
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bulk_net_* count: 20
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nets after cleanup: 6
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--- various reports ---
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input in2
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n2
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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--- property queries ---
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port clk: dir=input name=clk
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port in1: dir=input name=in1
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port in2: dir=input name=in2
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port out1: dir=output name=out1
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inst buf1: ref=BUF_X1 name=buf1
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inst and1: ref=AND2_X1 name=and1
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inst reg1: ref=DFF_X1 name=reg1
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pin buf1/A: dir=input name=buf1/A
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pin buf1/Z: dir=output name=buf1/Z
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pin and1/A1: dir=input name=and1/A1
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pin and1/A2: dir=input name=and1/A2
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pin and1/ZN: dir=output name=and1/ZN
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pin reg1/D: dir=input name=reg1/D
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pin reg1/CK: dir=input name=reg1/CK
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pin reg1/Q: dir=output name=reg1/Q
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net n1: name=n1
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net n2: name=n2
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