74 lines
1.5 KiB
Plaintext
74 lines
1.5 KiB
Plaintext
module verilog_complex_bus_test (clk,
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data_a,
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data_b,
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result,
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carry,
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overflow);
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input clk;
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input [7:0] data_a;
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input [7:0] data_b;
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output [7:0] result;
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output carry;
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output overflow;
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wire internal_carry;
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wire internal_overflow;
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wire [7:0] stage1;
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wire [7:0] stage2;
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AND2_X1 and0 (.A1(stage1[0]),
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.A2(data_b[0]),
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.ZN(stage2[0]));
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AND2_X1 and1 (.A1(stage1[1]),
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.A2(data_b[1]),
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.ZN(stage2[1]));
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AND2_X1 and2 (.A1(stage1[2]),
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.A2(data_b[2]),
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.ZN(stage2[2]));
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AND2_X1 and3 (.A1(stage1[3]),
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.A2(data_b[3]),
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.ZN(stage2[3]));
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AND2_X1 and4 (.A1(stage1[4]),
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.A2(data_b[4]),
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.ZN(stage2[4]));
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AND2_X1 and5 (.A1(stage1[5]),
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.A2(data_b[5]),
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.ZN(stage2[5]));
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AND2_X1 and6 (.A1(stage1[6]),
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.A2(data_b[6]),
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.ZN(stage2[6]));
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AND2_X1 and7 (.A1(stage1[7]),
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.A2(data_b[7]),
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.ZN(stage2[7]));
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AND2_X1 and_ovfl (.A1(stage2[7]),
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.A2(stage2[6]),
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.ZN(internal_overflow));
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OR2_X1 or_carry (.A1(stage2[7]),
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.A2(stage2[6]),
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.ZN(internal_carry));
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DFF_X1 reg0 (.D(stage2[0]),
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.CK(clk),
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.Q(result[0]));
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DFF_X1 reg1 (.D(stage2[1]),
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.CK(clk),
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.Q(result[1]));
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DFF_X1 reg2 (.D(stage2[2]),
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.CK(clk),
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.Q(result[2]));
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DFF_X1 reg3 (.D(stage2[3]),
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.CK(clk),
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.Q(result[3]));
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DFF_X1 reg4 (.D(stage2[4]),
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.CK(clk),
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.Q(result[4]));
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DFF_X1 reg5 (.D(stage2[5]),
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.CK(clk),
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.Q(result[5]));
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DFF_X1 reg6 (.D(stage2[6]),
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.CK(clk),
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.Q(result[6]));
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DFF_X1 reg7 (.D(stage2[7]),
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.CK(clk),
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.Q(result[7]));
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endmodule
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