619 lines
20 KiB
Plaintext
619 lines
20 KiB
Plaintext
--- slow_drivers ---
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slow drivers count: 3
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reg1
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and1
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buf1
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--- set_load (port ext pin cap) ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_load -wire_load ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_fanout_load ---
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Warning 461: search_network_sta_deep.tcl line 1, set_fanout_load not supported.
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_input_transition ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_drive ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_driving_cell ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- set_wire_load_mode ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- report_tags ---
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0 default ^min clk ^ clk_src clk crpr_pin null input in2
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1 default vmin clk ^ clk_src clk crpr_pin null input in2
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2 default ^max clk ^ clk_src clk crpr_pin null input in2
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3 default vmax clk ^ clk_src clk crpr_pin null input in2
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4 default ^min clk ^ clk_src clk crpr_pin null input in1
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5 default vmin clk ^ clk_src clk crpr_pin null input in1
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6 default ^max clk ^ clk_src clk crpr_pin null input in1
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7 default vmax clk ^ clk_src clk crpr_pin null input in1
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8 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
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9 default vmin clk ^ (clock ideal) clk_src clk crpr_pin null
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10 default ^min clk v (clock ideal) clk_src clk crpr_pin null
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11 default vmin clk v (clock ideal) clk_src clk crpr_pin null
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12 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
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13 default vmax clk ^ (clock ideal) clk_src clk crpr_pin null
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14 default ^max clk v (clock ideal) clk_src clk crpr_pin null
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15 default vmax clk v (clock ideal) clk_src clk crpr_pin null
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16 default ^min clk ^ clk_src clk crpr_pin null
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17 default vmin clk ^ clk_src clk crpr_pin null
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18 default ^max clk ^ clk_src clk crpr_pin null
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19 default vmax clk ^ clk_src clk crpr_pin null
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Longest hash bucket length 1 hash=6
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--- report_clk_infos ---
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default/min clk ^ clk_src clk
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default/max clk ^ clk_src clk
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default/min clk v clk_src clk
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default/max clk v clk_src clk
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4 clk infos
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--- report_tag_groups ---
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Group 0 hash = 2697898004198490802 ( 79)
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0 0 default ^min clk ^ clk_src clk crpr_pin null input in2
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1 2 default ^max clk ^ clk_src clk crpr_pin null input in2
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2 1 default vmin clk ^ clk_src clk crpr_pin null input in2
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3 3 default vmax clk ^ clk_src clk crpr_pin null input in2
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Group 1 hash = 17966741373156438452 ( 88)
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0 8 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
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1 12 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
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2 11 default vmin clk v (clock ideal) clk_src clk crpr_pin null
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3 15 default vmax clk v (clock ideal) clk_src clk crpr_pin null
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Group 2 hash = 17969506314027398258 ( 127)
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0 16 default ^min clk ^ clk_src clk crpr_pin null
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1 18 default ^max clk ^ clk_src clk crpr_pin null
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2 17 default vmin clk ^ clk_src clk crpr_pin null
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3 19 default vmax clk ^ clk_src clk crpr_pin null
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Longest hash bucket length 1 hash=79
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--- report_path_count_histogram ---
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4 15
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--- tag/group/path counts ---
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tags: 20
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tag_groups: 3
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clk_infos: 4
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paths: 60
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--- report_tag_arrivals ---
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Vertex out1
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Group 2
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^ min 0.100 / -2.000 16 default clk ^ clk_src clk crpr_pin null
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v min 0.099 / -2.000 17 default clk ^ clk_src clk crpr_pin null
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^ max 0.100 / 8.000 18 default clk ^ clk_src clk crpr_pin null
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v max 0.099 / 8.000 19 default clk ^ clk_src clk crpr_pin null
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Vertex out1
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^ min 0.100 / -2.000 default clk ^ clk_src clk crpr_pin null
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v min 0.099 / -2.000 default clk ^ clk_src clk crpr_pin null
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^ max 0.100 / 8.000 default clk ^ clk_src clk crpr_pin null
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v max 0.099 / 8.000 default clk ^ clk_src clk crpr_pin null
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--- report_arrival_entries ---
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--- report_required_entries ---
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Level 40
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buf1/Z
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buf2/Z
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Level 10
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reg1/CK
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--- find_requireds ---
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--- report_annotated_delay ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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--- report_annotated_check ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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--- report_disabled_edges ---
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--- network editing ---
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new_net: new_net
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--- make_instance ---
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new_inst: new_buf
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--- connect_pin ---
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--- disconnect_pin ---
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--- disconnect_pin A ---
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--- delete_instance ---
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--- delete_net ---
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--- replace_cell ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- replace_cell back ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- write_verilog ---
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--- write_sdc ---
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--- vertex queries ---
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worst_arrival pin: out1
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worst_arrival arrival: 1.0032709385487948e-10
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worst_slack pin: out1
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worst_slack slack: 7.899672915812062e-9
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--- report_path_end header/footer ---
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Warning 502: search_network_sta_deep.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead.
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.02 0.10 v buf2/Z (BUF_X1)
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0.00 0.10 v out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.03 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFF_X1)
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1.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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8.91 slack (MET)
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--- json format ---
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{"checks": [
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{
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"type": "output_delay",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "reg1/Q",
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"endpoint": "out1",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/Q",
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"net": "n3",
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"arrival": 8.371e-11,
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"capacitance": 9.747e-16,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 1.500e-17,
|
|
"slew": 3.668e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.668e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|
|
--- set_report_path_field_properties ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
--- report_checks -path_delay min_max ---
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ in2 (in)
|
|
0.03 1.03 ^ and1/ZN (AND2_X1)
|
|
0.02 1.05 ^ buf1/Z (BUF_X1)
|
|
0.00 1.05 ^ reg1/D (DFF_X1)
|
|
1.05 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
1.04 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|