1009 lines
34 KiB
Plaintext
1009 lines
34 KiB
Plaintext
--- set_false_path -from port -to pin ---
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No paths found.
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--- remove false path ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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8.91 slack (MET)
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--- set_false_path -through ---
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.50 0.50 ^ input external delay
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0.00 0.50 ^ rst (in)
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0.00 0.50 ^ reg1/RN (DFFR_X1)
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0.50 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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0.05 10.05 library recovery time
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10.05 data required time
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---------------------------------------------------------
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10.05 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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9.55 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFFR_X1)
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0.10 0.10 ^ reg1/Q (DFFR_X1)
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0.02 0.12 ^ buf2/Z (BUF_X1)
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0.00 0.12 ^ out1 (out)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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7.88 slack (MET)
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--- remove false_path through ---
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.50 0.50 ^ input external delay
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0.00 0.50 ^ rst (in)
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0.00 0.50 ^ reg1/RN (DFFR_X1)
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0.50 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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0.05 10.05 library recovery time
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10.05 data required time
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---------------------------------------------------------
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10.05 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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9.55 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFFR_X1)
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0.10 0.10 ^ reg1/Q (DFFR_X1)
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0.02 0.12 ^ buf2/Z (BUF_X1)
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0.00 0.12 ^ out1 (out)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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7.88 slack (MET)
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--- set_false_path -setup ---
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.50 0.50 ^ input external delay
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0.00 0.50 ^ rst (in)
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0.00 0.50 ^ reg1/RN (DFFR_X1)
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0.50 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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0.05 10.05 library recovery time
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10.05 data required time
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---------------------------------------------------------
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10.05 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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9.55 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFFR_X1)
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0.10 0.10 ^ reg1/Q (DFFR_X1)
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0.02 0.12 ^ buf2/Z (BUF_X1)
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0.00 0.12 ^ out1 (out)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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7.88 slack (MET)
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--- remove false_path setup ---
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--- set_false_path -hold ---
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (removal check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.50 0.50 ^ input external delay
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0.00 0.50 ^ rst (in)
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0.00 0.50 ^ reg1/RN (DFFR_X1)
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0.50 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFFR_X1)
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0.18 0.18 library removal time
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0.18 data required time
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---------------------------------------------------------
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0.18 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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0.32 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFFR_X1)
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0.08 0.08 v reg1/Q (DFFR_X1)
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0.00 0.08 v reg2/D (DFFR_X1)
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0.08 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFFR_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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--- remove false_path hold ---
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--- set_multicycle_path 2 -setup ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg1/CK (DFFR_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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18.91 slack (MET)
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--- set_multicycle_path 1 -hold ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFFR_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFFR_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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--- set_multicycle_path 3 -setup with -through ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in2 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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30.00 30.00 clock clk (rise edge)
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0.00 30.00 clock network delay (ideal)
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0.00 30.00 clock reconvergence pessimism
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30.00 ^ reg1/CK (DFFR_X1)
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-0.04 29.96 library setup time
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29.96 data required time
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---------------------------------------------------------
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29.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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28.91 slack (MET)
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--- remove multicycle through ---
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--- set_max_delay ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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5.00 5.00 max_delay
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0.00 5.00 clock reconvergence pessimism
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-0.04 4.96 library setup time
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4.96 data required time
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---------------------------------------------------------
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4.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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3.91 slack (MET)
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--- set_min_delay ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFFR_X1)
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1.04 data arrival time
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0.10 0.10 min_delay
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0.00 0.10 clock reconvergence pessimism
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0.00 0.10 library hold time
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0.10 data required time
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---------------------------------------------------------
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0.10 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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0.94 slack (MET)
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--- remove max/min delay ---
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.50 0.50 ^ input external delay
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0.00 0.50 ^ rst (in)
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0.00 0.50 ^ reg1/RN (DFFR_X1)
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0.50 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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0.05 10.05 library recovery time
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10.05 data required time
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---------------------------------------------------------
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10.05 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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9.55 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFFR_X1)
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0.10 0.10 ^ reg1/Q (DFFR_X1)
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0.02 0.12 ^ buf2/Z (BUF_X1)
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0.00 0.12 ^ out1 (out)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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7.88 slack (MET)
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--- set_max_delay -through ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in2 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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8.91 slack (MET)
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--- remove max_delay through ---
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--- group_path -name from_in1 ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: from_in1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFFR_X1)
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1.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFFR_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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8.91 slack (MET)
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Startpoint: rst (input port clocked by clk)
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Endpoint: reg1 (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.50 0.50 ^ input external delay
|
|
0.00 0.50 ^ rst (in)
|
|
0.00 0.50 ^ reg1/RN (DFFR_X1)
|
|
0.50 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
0.05 10.05 library recovery time
|
|
10.05 data required time
|
|
---------------------------------------------------------
|
|
10.05 data required time
|
|
-0.50 data arrival time
|
|
---------------------------------------------------------
|
|
9.55 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg1/Q (DFFR_X1)
|
|
0.02 0.12 ^ buf2/Z (BUF_X1)
|
|
0.00 0.12 ^ out1 (out)
|
|
0.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
7.88 slack (MET)
|
|
|
|
|
|
--- group_path -name to_out1 ---
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: from_in1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.02 1.02 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFFR_X1)
|
|
1.05 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
8.91 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: to_out1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg1/Q (DFFR_X1)
|
|
0.02 0.12 ^ buf2/Z (BUF_X1)
|
|
0.00 0.12 ^ out1 (out)
|
|
0.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
7.88 slack (MET)
|
|
|
|
|
|
Startpoint: rst (input port clocked by clk)
|
|
Endpoint: reg1 (recovery check against rising-edge clock clk)
|
|
Path Group: asynchronous
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.50 0.50 ^ input external delay
|
|
0.00 0.50 ^ rst (in)
|
|
0.00 0.50 ^ reg1/RN (DFFR_X1)
|
|
0.50 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
0.05 10.05 library recovery time
|
|
10.05 data required time
|
|
---------------------------------------------------------
|
|
10.05 data required time
|
|
-0.50 data arrival time
|
|
---------------------------------------------------------
|
|
9.55 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out2 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg2/Q (DFFR_X1)
|
|
0.02 0.11 ^ buf3/Z (BUF_X1)
|
|
0.00 0.11 ^ out2 (out)
|
|
0.11 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.11 data arrival time
|
|
---------------------------------------------------------
|
|
7.89 slack (MET)
|
|
|
|
|
|
--- group_path -name through_buf ---
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: from_in1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.02 1.02 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFFR_X1)
|
|
1.05 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
8.91 slack (MET)
|
|
|
|
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: through_buf
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in2 (in)
|
|
0.02 1.02 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFFR_X1)
|
|
1.05 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
8.91 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: to_out1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg1/Q (DFFR_X1)
|
|
0.02 0.12 ^ buf2/Z (BUF_X1)
|
|
0.00 0.12 ^ out1 (out)
|
|
0.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
7.88 slack (MET)
|
|
|
|
|
|
Startpoint: rst (input port clocked by clk)
|
|
Endpoint: reg1 (recovery check against rising-edge clock clk)
|
|
Path Group: asynchronous
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.50 0.50 ^ input external delay
|
|
0.00 0.50 ^ rst (in)
|
|
0.00 0.50 ^ reg1/RN (DFFR_X1)
|
|
0.50 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
0.05 10.05 library recovery time
|
|
10.05 data required time
|
|
---------------------------------------------------------
|
|
10.05 data required time
|
|
-0.50 data arrival time
|
|
---------------------------------------------------------
|
|
9.55 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out2 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg2/Q (DFFR_X1)
|
|
0.02 0.11 ^ buf3/Z (BUF_X1)
|
|
0.00 0.11 ^ out2 (out)
|
|
0.11 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.11 data arrival time
|
|
---------------------------------------------------------
|
|
7.89 slack (MET)
|
|
|
|
|
|
--- report_checks -path_group ---
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: from_in1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.02 1.02 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFFR_X1)
|
|
1.05 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFFR_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
8.91 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: to_out1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFFR_X1)
|
|
0.10 0.10 ^ reg1/Q (DFFR_X1)
|
|
0.02 0.12 ^ buf2/Z (BUF_X1)
|
|
0.00 0.12 ^ out1 (out)
|
|
0.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
7.88 slack (MET)
|
|
|
|
|
|
--- path_group_names ---
|
|
Path group names: clk from_in1 through_buf to_out1 asynchronous {path delay} {gated clock} unconstrained
|
|
--- report_check_types -max_delay ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
from_in1 8.91
|
|
through_buf 8.91
|
|
to_out1 7.88
|
|
clk 7.89
|
|
|
|
--- report_check_types -min_delay ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
from_in1 1.04
|
|
through_buf 1.04
|
|
to_out1 2.11
|
|
clk 0.08
|
|
|
|
--- report_check_types -recovery ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
asynchronous 9.55
|
|
|
|
--- report_check_types -removal ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
asynchronous 0.32
|
|
|
|
--- report_check_types -max_delay -min_delay together ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
from_in1 1.04
|
|
through_buf 1.04
|
|
to_out1 2.11
|
|
clk 0.08
|
|
from_in1 8.91
|
|
through_buf 8.91
|
|
to_out1 7.88
|
|
clk 7.89
|
|
|
|
--- report_check_types -recovery -removal ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
asynchronous 0.32
|
|
asynchronous 9.55
|
|
|
|
--- report_check_types -clock_gating_setup ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
No paths found.
|
|
|
|
--- report_check_types -clock_gating_hold ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
No paths found.
|
|
|
|
--- report_check_types -clock_gating_setup -clock_gating_hold ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
No paths found.
|
|
|
|
--- report_check_types -min_pulse_width ---
|
|
Required Actual
|
|
Pin Width Width Slack
|
|
------------------------------------------------------------
|
|
reg1/CK (high) 0.06 5.00 4.94 (MET)
|
|
|
|
--- report_check_types -min_period ---
|
|
--- report_check_types -max_skew ---
|
|
--- report_check_types -max_slew ---
|
|
max slew
|
|
|
|
Pin Limit Slew Slack
|
|
------------------------------------------------------------
|
|
reg1/Q 0.20 0.01 0.19 (MET)
|
|
|
|
--- report_check_types -max_capacitance ---
|
|
max capacitance
|
|
|
|
Pin Limit Cap Slack
|
|
------------------------------------------------------------
|
|
reg1/Q 60.58 2.10 58.47 (MET)
|
|
|
|
--- report_check_types -max_fanout ---
|
|
--- report_check_types -violators ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
No paths found.
|
|
|
|
--- report_check_types -violators -verbose ---
|
|
No paths found.
|
|
--- worst_clock_skew -setup ---
|
|
worst_clock_skew setup: 0.0
|
|
--- worst_clock_skew -hold ---
|
|
worst_clock_skew hold: 0.0
|
|
--- total_negative_slack -max ---
|
|
tns max: 0.0
|
|
--- total_negative_slack -min ---
|
|
tns min: 0.0
|
|
--- worst_slack -max ---
|
|
worst_slack max: 7.881454822969938
|
|
--- worst_slack -min ---
|
|
worst_slack min: 0.08220570290497634
|
|
--- worst_negative_slack -max ---
|
|
wns max: 0.0
|
|
--- endpoint_slack ---
|
|
endpoint_slack out1 clk max: Inf
|
|
--- report_path -min ---
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ in1 (in)
|
|
0.02 1.02 ^ and1/ZN (AND2_X1)
|
|
0.02 1.04 ^ buf1/Z (BUF_X1)
|
|
0.00 1.04 ^ reg1/D (DFFR_X1)
|
|
--- report_path -max ---
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in2 (in)
|
|
0.02 1.02 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFFR_X1)
|
|
--- report_arrival ---
|
|
(clk ^) r 1.04:1.05 f 1.05:1.05
|
|
--- report_required ---
|
|
(clk ^) r 0.00:9.97 f 0.00:9.96
|
|
--- report_slack ---
|
|
(clk ^) r 1.04:8.92 f 1.04:8.91
|