21 lines
711 B
Verilog
21 lines
711 B
Verilog
module search_check_timing (clk, clk2, in1, in2, in3, in_unconst, out1, out2, out_unconst);
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input clk, clk2, in1, in2, in3, in_unconst;
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output out1, out2, out_unconst;
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wire n1, n2, n3, n4, n5, n6, n7;
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// Normal path
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AND2_X1 and1 (.A1(in1), .A2(in2), .ZN(n1));
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BUF_X1 buf1 (.A(n1), .Z(n2));
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DFF_X1 reg1 (.D(n2), .CK(clk), .Q(n3));
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BUF_X1 buf2 (.A(n3), .Z(out1));
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// Register with second clock (multiple clocks scenario)
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DFF_X1 reg2 (.D(n3), .CK(clk2), .Q(n4));
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BUF_X1 buf3 (.A(n4), .Z(out2));
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// Unconstrained path (no set_output_delay on out_unconst)
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BUF_X1 buf4 (.A(in_unconst), .Z(n5));
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DFF_X1 reg3 (.D(n5), .CK(clk), .Q(n6));
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BUF_X1 buf5 (.A(n6), .Z(out_unconst));
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endmodule
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