410 lines
19 KiB
Plaintext
410 lines
19 KiB
Plaintext
--- read_sdf with timing checks ---
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--- report_checks with SDF ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.13 0.69 v nor1/ZN (NOR2_X1)
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0.03 0.72 v reg3/D (DFF_X1)
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0.72 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.72 data arrival time
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---------------------------------------------------------
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9.25 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.02 0.02 v nand1/ZN (NAND2_X1)
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0.01 0.03 v reg2/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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-0.02 slack (VIOLATED)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.13 0.69 v nor1/ZN (NOR2_X1)
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0.03 0.72 v reg3/D (DFF_X1)
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0.72 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.72 data arrival time
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---------------------------------------------------------
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9.25 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.13 0.69 v nor1/ZN (NOR2_X1)
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0.03 0.72 v reg3/D (DFF_X1)
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0.72 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.72 data arrival time
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---------------------------------------------------------
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9.25 slack (MET)
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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--- report_annotated_delay ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 11 11 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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37 28 9
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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----------------------------------------------------------------
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17 17 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 11 11 0
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----------------------------------------------------------------
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11 11 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 6 0 6
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----------------------------------------------------------------
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6 0 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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3 0 3
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 11 11 0
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----------------------------------------------------------------
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28 28 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 11 11 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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37 28 9
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> or1/A2
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> inv1/A
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internal net buf1/Z -> and1/A1
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delay buf2/A -> buf2/Z
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internal net buf2/Z -> and1/A2
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> or1/A1
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internal net inv1/ZN -> nor1/A1
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delay nand1/A1 -> nand1/ZN
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delay nand1/A2 -> nand1/ZN
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internal net nand1/ZN -> nor1/A2
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internal net nand1/ZN -> reg2/D
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delay nor1/A1 -> nor1/ZN
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delay nor1/A2 -> nor1/ZN
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internal net nor1/ZN -> reg3/D
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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internal net or1/ZN -> nand1/A1
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internal net or1/ZN -> reg1/D
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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delay reg2/CK -> reg2/QN
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delay reg2/CK -> reg2/Q
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delay reg3/CK -> reg3/QN
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delay reg3/CK -> reg3/Q
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 11 11 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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37 28 9
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net clk -> reg2/CK
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primary input net clk -> reg3/CK
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primary input net d1 -> buf1/A
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primary input net d2 -> buf2/A
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primary input net en -> nand1/A2
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primary output net reg1/Q -> q1
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primary output net reg2/Q -> q2
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primary output net reg3/Q -> q3
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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constant arcs 0 0
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internal net arcs 11 11 0
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constant arcs 0 0
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net arcs from primary inputs 6 0 6
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constant arcs 0 0
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net arcs to primary outputs 3 0 3
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constant arcs 0 0
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----------------------------------------------------------------
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37 28 9
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 11 11 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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37 28 9
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--- report_annotated_check ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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6 6 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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6 6 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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Annotated Arcs
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width reg1/CK -> reg1/CK
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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width reg2/CK -> reg2/CK
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setup reg2/CK -> reg2/D
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hold reg2/CK -> reg2/D
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width reg3/CK -> reg3/CK
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setup reg3/CK -> reg3/D
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hold reg3/CK -> reg3/D
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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Unannotated Arcs
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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constant arcs 0 0
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cell hold arcs 3 3 0
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constant arcs 0 0
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cell width arcs 3 3 0
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constant arcs 0 0
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----------------------------------------------------------------
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9 9 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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--- write_sdf ---
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--- re-read SDF ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.13 0.69 v nor1/ZN (NOR2_X1)
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0.03 0.72 v reg3/D (DFF_X1)
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0.72 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.72 data arrival time
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---------------------------------------------------------
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9.25 slack (MET)
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