480 lines
21 KiB
Plaintext
480 lines
21 KiB
Plaintext
--- Test 1: read SDF with DEVICE/edge checks ---
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Warning 192: sdf_test5.sdf line 106, cell DFF_X1 CK -> D skew check not found.
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--- Test 2: timing paths ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d1 (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.05 0.32 v or1/ZN (OR2_X1)
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0.13 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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---------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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---------------------------------------------------------
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9.42 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.02 0.02 v nand1/ZN (NAND2_X1)
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0.01 0.03 v reg2/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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-0.02 slack (VIOLATED)
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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--- Test 3: annotated reports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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internal net arcs 9 9 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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33 22 11
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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----------------------------------------------------------------
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15 13 2
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 9 9 0
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----------------------------------------------------------------
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9 9 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 6 0 6
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----------------------------------------------------------------
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6 0 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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3 0 3
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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internal net arcs 9 9 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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33 22 11
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> or1/A2
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internal net and1/ZN -> reg3/D
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> inv1/A
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internal net buf1/Z -> and1/A1
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delay buf2/A -> buf2/Z
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internal net buf2/Z -> and1/A2
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> or1/A1
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delay nand1/A1 -> nand1/ZN
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delay nand1/A2 -> nand1/ZN
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internal net nand1/ZN -> reg2/D
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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internal net or1/ZN -> nand1/A1
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internal net or1/ZN -> reg1/D
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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delay reg2/CK -> reg2/Q
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delay reg3/CK -> reg3/Q
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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internal net arcs 9 9 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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33 22 11
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net clk -> reg2/CK
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primary input net clk -> reg3/CK
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primary input net d1 -> buf1/A
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primary input net d2 -> buf2/A
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primary input net en -> nand1/A2
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primary output net reg1/Q -> q1
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delay reg2/CK -> reg2/QN
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primary output net reg2/Q -> q2
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delay reg3/CK -> reg3/QN
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primary output net reg3/Q -> q3
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 3 1 2
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----------------------------------------------------------------
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3 1 2
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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cell width arcs 3 1 2
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----------------------------------------------------------------
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9 7 2
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--- Test 4: write SDF ---
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--- Test 5: incremental SDF ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d1 (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.05 0.32 v or1/ZN (OR2_X1)
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0.13 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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---------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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---------------------------------------------------------
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9.42 slack (MET)
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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internal net arcs 9 9 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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33 22 11
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 15 13 2
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internal net arcs 9 9 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 3 0 3
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----------------------------------------------------------------
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33 22 11
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> or1/A2
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internal net and1/ZN -> reg3/D
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> inv1/A
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internal net buf1/Z -> and1/A1
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delay buf2/A -> buf2/Z
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internal net buf2/Z -> and1/A2
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> or1/A1
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delay nand1/A1 -> nand1/ZN
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delay nand1/A2 -> nand1/ZN
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internal net nand1/ZN -> reg2/D
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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internal net or1/ZN -> nand1/A1
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internal net or1/ZN -> reg1/D
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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delay reg2/CK -> reg2/Q
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delay reg3/CK -> reg3/Q
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--- Test 6: re-read absolute SDF ---
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Warning 192: sdf_test5.sdf line 106, cell DFF_X1 CK -> D skew check not found.
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d1 (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.05 0.32 v or1/ZN (OR2_X1)
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0.13 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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---------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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---------------------------------------------------------
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9.42 slack (MET)
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 3 3 0
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cell hold arcs 3 3 0
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----------------------------------------------------------------
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6 6 0
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--- Test 7: detailed reports ---
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Warning 168: sdf_device_cond.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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1 0.97 0.10 0.00 0.00 ^ d1 (in)
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0.10 0.00 0.00 ^ buf1/A (BUF_X1)
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2 2.62 0.01 0.15 0.15 ^ buf1/Z (BUF_X1)
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0.01 0.03 0.18 ^ inv1/A (INV_X1)
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1 0.79 0.00 0.09 0.27 v inv1/ZN (INV_X1)
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0.00 0.02 0.29 v or1/A1 (OR2_X1)
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2 2.59 0.01 0.03 0.32 v or1/ZN (OR2_X1)
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0.01 0.03 0.35 v nand1/A1 (NAND2_X1)
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1 1.14 0.02 0.10 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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-----------------------------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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-----------------------------------------------------------------------------
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9.42 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d1 (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.05 0.32 v or1/ZN (OR2_X1)
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0.13 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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---------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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---------------------------------------------------------
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9.42 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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-----------------------------------------------------------------
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0.000000 0.000000 clock clk (rise edge)
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0.000000 0.000000 clock network delay (ideal)
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0.000000 0.000000 ^ input external delay
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0.000000 0.000000 ^ d1 (in)
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0.150000 0.150000 ^ buf1/Z (BUF_X1)
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0.120000 0.270000 v inv1/ZN (INV_X1)
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0.050000 0.320000 v or1/ZN (OR2_X1)
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0.130000 0.450000 ^ nand1/ZN (NAND2_X1)
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0.020000 0.470000 ^ reg2/D (DFF_X1)
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0.470000 data arrival time
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10.000000 10.000000 clock clk (rise edge)
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0.000000 10.000000 clock network delay (ideal)
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0.000000 10.000000 clock reconvergence pessimism
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10.000000 ^ reg2/CK (DFF_X1)
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-0.110000 9.890000 library setup time
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9.890000 data required time
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-----------------------------------------------------------------
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9.890000 data required time
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-0.470000 data arrival time
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-----------------------------------------------------------------
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9.420000 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d1 (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 v inv1/ZN (INV_X1)
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0.05 0.32 v or1/ZN (OR2_X1)
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0.13 0.45 ^ nand1/ZN (NAND2_X1)
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0.02 0.47 ^ reg2/D (DFF_X1)
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0.47 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.11 9.89 library setup time
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9.89 data required time
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---------------------------------------------------------
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9.89 data required time
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-0.47 data arrival time
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---------------------------------------------------------
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9.42 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.02 0.02 v nand1/ZN (NAND2_X1)
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0.01 0.03 v reg2/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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-0.02 slack (VIOLATED)
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