304 lines
15 KiB
Plaintext
304 lines
15 KiB
Plaintext
--- read_sdf test2 (with timing checks/interconnects) ---
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--- report_annotated_delay -cell ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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----------------------------------------------------------------
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6 6 0
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--- report_annotated_delay -net ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 3 3 0
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----------------------------------------------------------------
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3 3 0
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--- report_annotated_delay -from_in_ports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 3 0 3
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----------------------------------------------------------------
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3 0 3
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--- report_annotated_delay -to_out_ports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_delay -cell -net combined ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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----------------------------------------------------------------
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9 9 0
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--- report_annotated_delay -report_annotated ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 9 4
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> reg1/D
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> buf2/A
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delay buf2/A -> buf2/Z
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internal net buf2/Z -> and1/A1
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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--- report_annotated_delay -report_unannotated ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 9 4
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net d -> buf1/A
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primary input net en -> and1/A2
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primary output net reg1/Q -> q
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--- report_annotated_delay -constant_arcs ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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constant arcs 0 0
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internal net arcs 3 3 0
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constant arcs 0 0
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net arcs from primary inputs 3 0 3
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constant arcs 0 0
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net arcs to primary outputs 1 0 1
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constant arcs 0 0
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----------------------------------------------------------------
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13 9 4
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--- report_annotated_delay -max_lines 2 ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 9 4
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--- report_annotated_check -setup ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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--- report_annotated_check -hold ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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--- report_annotated_check -recovery ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -removal ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -width ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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--- report_annotated_check -period ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -nochange ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -max_skew ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -setup -report_annotated ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Annotated Arcs
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setup reg1/CK -> reg1/D
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--- report_annotated_check -setup -report_unannotated ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Unannotated Arcs
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--- report_annotated_check -setup -hold combined ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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2 2 0
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--- report_annotated_check all types ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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--- report_annotated_check -constant_arcs ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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constant arcs 0 0
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cell hold arcs 1 1 0
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constant arcs 0 0
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cell width arcs 1 1 0
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constant arcs 0 0
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----------------------------------------------------------------
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3 3 0
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--- report_annotated_check -max_lines 3 ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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--- write_sdf default ---
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--- write_sdf -divider . ---
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--- write_sdf -digits 6 ---
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--- write_sdf -include_typ ---
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--- write_sdf -no_timestamp ---
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--- write_sdf -no_version ---
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--- write_sdf -gzip ---
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--- write_sdf combined options ---
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--- report_checks (SDF annotated) ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 ^ buf2/Z (BUF_X2)
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0.15 0.42 ^ and1/ZN (AND2_X1)
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0.03 0.45 ^ reg1/D (DFF_X1)
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0.45 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.10 9.90 library setup time
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9.90 data required time
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---------------------------------------------------------
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9.90 data required time
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-0.45 data arrival time
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---------------------------------------------------------
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9.45 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.04 0.04 ^ and1/ZN (AND2_X1)
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0.01 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.00 slack (VIOLATED)
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 ^ buf2/Z (BUF_X2)
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0.15 0.42 ^ and1/ZN (AND2_X1)
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0.03 0.45 ^ reg1/D (DFF_X1)
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0.45 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.10 9.90 library setup time
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9.90 data required time
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---------------------------------------------------------
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9.90 data required time
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-0.45 data arrival time
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---------------------------------------------------------
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9.45 slack (MET)
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