240 lines
7.5 KiB
Tcl
240 lines
7.5 KiB
Tcl
# Test escaped names, path dividers, and SDC network queries.
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# Targets:
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# SdcNetwork.cc: findPort, findPin, findNet with hierarchy,
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# escapeDividers, escapeBrackets, portDirection, makePort,
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# findInstancesMatching, findPinsHierMatching
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# Network.cc: pathDivider, pathEscape, setPathDivider, setPathEscape,
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# pathName with escaped chars, findInstanceRelative
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# ParseBus.cc: parseBusName edge cases (escaped names, bus bit ranges,
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# isBusName, wildcard subscripts)
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# ConcreteNetwork.cc: findPort, groupBusPorts, setAttribute/getAttribute
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog network_test1.v
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link_design network_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_input_delay -clock clk 0 [get_ports in2]
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set_output_delay -clock clk 0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks
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#---------------------------------------------------------------
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# Test various pattern matching
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# Exercises: findInstancesMatching with different patterns
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#---------------------------------------------------------------
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puts "--- pattern matching ---"
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# Star pattern
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set star_cells [get_cells *]
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puts "cells *: [llength $star_cells]"
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# Question mark pattern
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set q_cells [get_cells ???1]
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puts "cells ???1: [llength $q_cells]"
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# Prefix pattern
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set prefix_cells [get_cells {b*}]
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puts "cells b*: [llength $prefix_cells]"
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# Specific prefix
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set buf_cells [get_cells buf*]
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puts "cells buf*: [llength $buf_cells]"
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set and_cells [get_cells and*]
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puts "cells and*: [llength $and_cells]"
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set reg_cells [get_cells reg*]
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puts "cells reg*: [llength $reg_cells]"
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# Non-matching pattern
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set x_cells [get_cells nonexistent_*]
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puts "cells nonexistent_*: [llength $x_cells]"
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#---------------------------------------------------------------
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# Test get_pins with various patterns
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# Exercises: findPinsMatching, findInstPinsMatching
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#---------------------------------------------------------------
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puts "--- pin pattern matching ---"
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set buf_pins [get_pins buf1/*]
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puts "buf1/* pins: [llength $buf_pins]"
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set all_a_pins [get_pins */A]
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puts "*/A pins: [llength $all_a_pins]"
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set all_z_pins [get_pins */Z]
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puts "*/Z pins: [llength $all_z_pins]"
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set all_zn_pins [get_pins */ZN]
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puts "*/ZN pins: [llength $all_zn_pins]"
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set all_ck_pins [get_pins */CK]
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puts "*/CK pins: [llength $all_ck_pins]"
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set hier_pins [get_pins -hierarchical *]
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puts "hier pins: [llength $hier_pins]"
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# Wildcard on inst
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set star_a_pins [get_pins */*1]
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puts "*/*1 pins: [llength $star_a_pins]"
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#---------------------------------------------------------------
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# Test get_nets with patterns
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# Exercises: findNetsMatching
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#---------------------------------------------------------------
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puts "--- net pattern matching ---"
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set all_nets [get_nets *]
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puts "all nets: [llength $all_nets]"
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set n_nets [get_nets n*]
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puts "n* nets: [llength $n_nets]"
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set hier_nets [get_nets -hierarchical *]
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puts "hier nets: [llength $hier_nets]"
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#---------------------------------------------------------------
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# Test get_ports patterns
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# Exercises: findPortsMatching (non-bus path)
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#---------------------------------------------------------------
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puts "--- port pattern matching ---"
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set all_ports [get_ports *]
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puts "all ports: [llength $all_ports]"
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set i_ports [get_ports in*]
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puts "in* ports: [llength $i_ports]"
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set o_ports [get_ports out*]
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puts "out* ports: [llength $o_ports]"
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set c_ports [get_ports clk*]
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puts "clk* ports: [llength $c_ports]"
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# Pattern with ? wildcard
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set q_ports [get_ports {?n?}]
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puts "?n? ports: [llength $q_ports]"
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#---------------------------------------------------------------
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# Test get_lib_cells with patterns across libraries
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# Exercises: findLibCellsMatching
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#---------------------------------------------------------------
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puts "--- lib cell pattern matching ---"
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set all_lib_cells [get_lib_cells NangateOpenCellLibrary/*]
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puts "all lib cells: [llength $all_lib_cells]"
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set inv_lib_cells [get_lib_cells NangateOpenCellLibrary/INV*]
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puts "INV* lib cells: [llength $inv_lib_cells]"
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set buf_lib_cells [get_lib_cells NangateOpenCellLibrary/BUF*]
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puts "BUF* lib cells: [llength $buf_lib_cells]"
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set nand_lib_cells [get_lib_cells NangateOpenCellLibrary/NAND*]
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puts "NAND* lib cells: [llength $nand_lib_cells]"
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# Wildcard library
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set all_all [get_lib_cells */*]
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puts "*/* lib cells: [llength $all_all]"
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# Specific library search
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set star_star [get_lib_cells */INV*]
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puts "*/INV* lib cells: [llength $star_star]"
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set star_dff [get_lib_cells */DFF*]
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puts "*/DFF* lib cells: [llength $star_dff]"
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set star_aoi [get_lib_cells */AOI*]
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puts "*/AOI* lib cells: [llength $star_aoi]"
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set star_oai [get_lib_cells */OAI*]
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puts "*/OAI* lib cells: [llength $star_oai]"
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set star_mux [get_lib_cells */MUX*]
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puts "*/MUX* lib cells: [llength $star_mux]"
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set star_sdff [get_lib_cells */SDFF*]
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puts "*/SDFF* lib cells: [llength $star_sdff]"
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set star_fill [get_lib_cells */FILL*]
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puts "*/FILL* lib cells: [llength $star_fill]"
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set star_clkgate [get_lib_cells */CLKGATE*]
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puts "*/CLKGATE* lib cells: [llength $star_clkgate]"
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set star_tlat [get_lib_cells */TLAT*]
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puts "*/TLAT* lib cells: [llength $star_tlat]"
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set star_tinv [get_lib_cells */TINV*]
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puts "*/TINV* lib cells: [llength $star_tinv]"
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#---------------------------------------------------------------
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# Test get_lib_pins patterns
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# Exercises: findLibPinsMatching
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#---------------------------------------------------------------
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puts "--- lib pin pattern matching ---"
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set inv_lib_pins [get_lib_pins NangateOpenCellLibrary/INV_X1/*]
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puts "INV_X1/* lib pins: [llength $inv_lib_pins]"
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set buf_lib_pins [get_lib_pins NangateOpenCellLibrary/BUF_X1/*]
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puts "BUF_X1/* lib pins: [llength $buf_lib_pins]"
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set dff_lib_pins [get_lib_pins NangateOpenCellLibrary/DFF_X1/*]
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puts "DFF_X1/* lib pins: [llength $dff_lib_pins]"
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set nand_lib_pins [get_lib_pins NangateOpenCellLibrary/NAND2_X1/*]
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puts "NAND2_X1/* lib pins: [llength $nand_lib_pins]"
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set aoi_lib_pins [get_lib_pins NangateOpenCellLibrary/AOI21_X1/*]
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puts "AOI21_X1/* lib pins: [llength $aoi_lib_pins]"
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set sdff_lib_pins [get_lib_pins NangateOpenCellLibrary/SDFF_X1/*]
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puts "SDFF_X1/* lib pins: [llength $sdff_lib_pins]"
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set clkgate_lib_pins [get_lib_pins NangateOpenCellLibrary/CLKGATETST_X1/*]
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puts "CLKGATETST_X1/* lib pins: [llength $clkgate_lib_pins]"
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set fa_lib_pins [get_lib_pins NangateOpenCellLibrary/FA_X1/*]
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puts "FA_X1/* lib pins: [llength $fa_lib_pins]"
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#---------------------------------------------------------------
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# Test current_design
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#---------------------------------------------------------------
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puts "--- current_design ---"
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set design [current_design]
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puts "current_design: $design"
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#---------------------------------------------------------------
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# Test extensive timing reports
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# Exercises: timing traversal, path reporting
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#---------------------------------------------------------------
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puts "--- timing reports ---"
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report_checks
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report_checks -path_delay min
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report_checks -path_delay max
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report_checks -from [get_ports in1]
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report_checks -from [get_ports in2]
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report_checks -to [get_ports out1]
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report_checks -rise_from [get_ports in1]
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report_checks -fall_from [get_ports in1]
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report_checks -rise_to [get_ports out1]
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report_checks -fall_to [get_ports out1]
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# Various report formats
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -format full_clock
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report_checks -format full_clock_expanded
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report_checks -digits 6
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report_checks -no_line_splits
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# Check types
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report_check_types -max_delay -min_delay
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report_check_types -max_slew -max_capacitance -max_fanout
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# Report power
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report_power
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