73 lines
2.1 KiB
Tcl
73 lines
2.1 KiB
Tcl
# Test SPICE write with additional options
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog spice_test1.v
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link_design spice_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_output_delay -clock clk 1.0 [get_ports out1]
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puts "--- report_checks ---"
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report_checks
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# Create mock SPICE files
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set spice_dir [make_result_file spice_opts_out]
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file mkdir $spice_dir
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set model_file [file join $spice_dir mock_model.sp]
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set model_fh [open $model_file w]
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puts $model_fh "* Mock SPICE model file"
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puts $model_fh ".model nmos nmos level=1"
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puts $model_fh ".model pmos pmos level=1"
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close $model_fh
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set subckt_file [file join $spice_dir mock_subckt.sp]
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set subckt_fh [open $subckt_file w]
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puts $subckt_fh "* Mock SPICE subckt file"
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puts $subckt_fh ".subckt BUF_X1 A Z VDD VSS"
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puts $subckt_fh "M1 Z A VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 Z A VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt BUF_X2 A Z VDD VSS"
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puts $subckt_fh "M1 Z A VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 Z A VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt DFF_X1 D CK Q QN VDD VSS"
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puts $subckt_fh "M1 Q D VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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close $subckt_fh
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puts "--- write_path_spice default ---"
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_file [file join $spice_dir spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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puts "--- write_path_spice with -simulator hspice ---"
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_file [file join $spice_dir spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS \
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-simulator hspice
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puts "--- write_path_spice with -simulator xyce ---"
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_file [file join $spice_dir spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS \
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-simulator xyce
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