OpenSTA/verilog
Jaehyun Kim 422f774b64 Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenSTA into secure-sta-test-by-opus
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-29 22:33:08 +09:00
..
test Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenSTA into secure-sta-test-by-opus 2026-03-29 22:33:08 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy use std::format squash 2026-03-16 15:01:38 -07:00
VerilogReader.cc use std::format squash 2026-03-16 15:01:38 -07:00
VerilogReaderPvt.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogScanner.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogWriter.cc use std::format squash 2026-03-16 15:01:38 -07:00