67 lines
2.1 KiB
Plaintext
67 lines
2.1 KiB
Plaintext
--- report_checks ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.04 1.10 v or1/ZN (OR2_X1)
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0.00 1.10 v reg2/D (DFF_X1)
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1.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.10 data arrival time
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---------------------------------------------------------
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8.86 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in2 (in)
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0.01 1.01 v inv1/ZN (INV_X1)
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0.03 1.04 v and1/ZN (AND2_X1)
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0.00 1.04 v reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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No paths found.
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No paths found.
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--- write_path_spice max ---
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--- write_path_spice min ---
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--- write_path_spice specific path ---
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--- write_path_spice hspice ---
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--- write_path_spice xyce ---
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