483 lines
20 KiB
Plaintext
483 lines
20 KiB
Plaintext
--- Test 1: read_sdf ---
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Warning 192: sdf_cond_pathpulse.sdf line 97, cell DFF_X1 CK -> D skew check not found.
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--- Test 2: timing paths ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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9.39 slack (MET)
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Startpoint: sel (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ sel (in)
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0.02 0.02 v nand1/ZN (NAND2_X1)
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0.01 0.03 v reg2/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.03 0.03 library hold time
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0.03 data required time
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---------------------------------------------------------
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0.03 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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0.00 slack (VIOLATED)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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9.39 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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9.39 slack (MET)
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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--- Test 3: annotated reports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 12 11 1
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internal net arcs 6 6 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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26 17 9
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 12 11 1
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----------------------------------------------------------------
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12 11 1
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 6 6 0
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----------------------------------------------------------------
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6 6 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 6 0 6
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----------------------------------------------------------------
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6 0 6
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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2 0 2
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 12 11 1
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internal net arcs 6 6 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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26 17 9
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> or1/A2
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> and1/A1
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> or1/A1
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delay nand1/A1 -> nand1/ZN
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delay nand1/A2 -> nand1/ZN
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internal net nand1/ZN -> reg2/D
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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internal net or1/ZN -> nand1/A1
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internal net or1/ZN -> reg1/D
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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delay reg2/CK -> reg2/Q
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 12 11 1
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internal net arcs 6 6 0
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net arcs from primary inputs 6 0 6
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net arcs to primary outputs 2 0 2
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----------------------------------------------------------------
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26 17 9
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net clk -> reg2/CK
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primary input net d1 -> buf1/A
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primary input net d2 -> inv1/A
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primary input net sel -> and1/A2
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primary input net sel -> nand1/A2
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primary output net reg1/Q -> q1
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delay reg2/CK -> reg2/QN
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primary output net reg2/Q -> q2
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--- Test 4: annotated checks ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 2 2 0
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----------------------------------------------------------------
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2 2 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 2 2 0
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----------------------------------------------------------------
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2 2 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 2 1 1
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----------------------------------------------------------------
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2 1 1
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 2 2 0
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cell hold arcs 2 2 0
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cell width arcs 2 1 1
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----------------------------------------------------------------
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6 5 1
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 2 2 0
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cell hold arcs 2 2 0
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cell width arcs 2 1 1
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----------------------------------------------------------------
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6 5 1
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Annotated Arcs
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width reg1/CK -> reg1/CK
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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setup reg2/CK -> reg2/D
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hold reg2/CK -> reg2/D
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 2 2 0
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cell hold arcs 2 2 0
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cell width arcs 2 1 1
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----------------------------------------------------------------
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6 5 1
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Unannotated Arcs
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width reg2/CK -> reg2/CK
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--- Test 5: write SDF ---
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--- Test 6: detailed reports ---
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Warning 168: sdf_cond_pathpulse.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.10 0.00 0.00 v d1 (in)
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0.10 0.00 0.00 v buf1/A (BUF_X1)
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1 0.87 0.01 0.14 0.14 v buf1/Z (BUF_X1)
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0.01 0.03 0.17 v and1/A1 (AND2_X1)
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1 0.90 0.01 0.13 0.30 v and1/ZN (AND2_X1)
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0.01 0.03 0.33 v or1/A2 (OR2_X1)
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2 2.59 0.01 0.10 0.43 v or1/ZN (OR2_X1)
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0.01 0.03 0.46 v nand1/A1 (NAND2_X1)
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1 1.14 0.02 0.10 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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-----------------------------------------------------------------------------
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9.39 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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-----------------------------------------------------------------
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0.000000 0.000000 clock clk (rise edge)
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0.000000 0.000000 clock network delay (ideal)
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0.000000 0.000000 v input external delay
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0.000000 0.000000 v d1 (in)
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0.140000 0.140000 v buf1/Z (BUF_X1)
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0.160000 0.300000 v and1/ZN (AND2_X1)
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0.130000 0.430000 v or1/ZN (OR2_X1)
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0.130000 0.560000 ^ nand1/ZN (NAND2_X1)
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0.020000 0.580000 ^ reg2/D (DFF_X1)
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0.580000 data arrival time
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10.000000 10.000000 clock clk (rise edge)
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0.000000 10.000000 clock network delay (ideal)
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0.000000 10.000000 clock reconvergence pessimism
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10.000000 ^ reg2/CK (DFF_X1)
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-0.030000 9.970000 library setup time
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9.970000 data required time
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-----------------------------------------------------------------
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9.970000 data required time
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-0.580000 data arrival time
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-----------------------------------------------------------------
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9.390000 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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9.39 slack (MET)
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Startpoint: sel (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ sel (in)
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0.02 0.02 v nand1/ZN (NAND2_X1)
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0.01 0.03 v reg2/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.03 0.03 library hold time
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0.03 data required time
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---------------------------------------------------------
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0.03 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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0.00 slack (VIOLATED)
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No paths found.
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No paths found.
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.60 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.40 slack (MET)
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Pin: reg1/CK
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10.00 period
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-1.00 min period
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---------------------------------------------------------
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9.00 slack (MET)
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--- Test 7: re-read SDF ---
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Warning 192: sdf_cond_pathpulse.sdf line 97, cell DFF_X1 CK -> D skew check not found.
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d1 (in)
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0.14 0.14 v buf1/Z (BUF_X1)
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0.16 0.30 v and1/ZN (AND2_X1)
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0.13 0.43 v or1/ZN (OR2_X1)
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0.13 0.56 ^ nand1/ZN (NAND2_X1)
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0.02 0.58 ^ reg2/D (DFF_X1)
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0.58 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.58 data arrival time
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---------------------------------------------------------
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9.39 slack (MET)
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--- Test 8: combined write ---
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